pinctrl/renesas/pinctrl-rzg2l.c

94  * n indicates number of pins in the port, a is the register index
216  * @func_base: base number for port function (see register PFC)
218  * @oen_max_port: the maximum port number supporting output enable
239  * @cfg: port pin configuration
240  * @port: port number
241  * @pin: port pin
245 	u32 port:5;
328 					      unsigned int port,
334 		if (pctrl->data->variable_pin_cfg[i].port == port &&
344 		.port = 20,
351 		.port = 20,
358 		.port = 20,
365 		.port = 20,
371 		.port = 20,
377 		.port = 20,
383 		.port = 20,
389 		.port = 20,
395 		.port = 23,
401 		.port = 23,
407 		.port = 23,
413 		.port = 23,
419 		.port = 23,
424 		.port = 24,
429 		.port = 24,
435 		.port = 24,
441 		.port = 24,
447 		.port = 24,
453 		.port = 24,
526 		dev_dbg(pctrl->dev, "port:%u pin: %u off:%x PSEL:%u\n",
785 				   u64 cfg, u32 port, u8 bit)
791 	if (!(pinmap & BIT(bit)) || port >= pctrl->data->n_port_pins)
794 	data = pctrl->data->port_pin_configs[port];
1136 		 * for 3V3 port source.
1395 	u32 port = RZG2L_PIN_ID_TO_PORT(offset);
1401 	ret = rzg2l_validate_gpio_pin(pctrl, *pin_data, port, bit);
1668 	/* Below additional port pins (P19 - P28) are exclusively available on RZ/Five SoC only */
1853 	u32 port, bit;
1858 	port = virq / 8;
1861 	if (port >= data->n_ports ||
1862 	    bit >= hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, data->port_pin_configs[port])))
1866 	for (i = 0; i < port; i++)
2123 		u32 port, bit;
2125 		port = offset / 8;
2128 		if (port >= pctrl->data->n_ports ||
2130 					      pctrl->data->port_pin_configs[port])))
2417 	for (u32 port = 0; port < nports; port++) {
2423 		cfg = pctrl->data->port_pin_configs[port];
2432 			RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PFC(off), cache->pfc[port]);
2438 		RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + PMC(off), cache->pmc[port]);
2441 						 cache->iolh[0][port]);
2444 							 cache->iolh[1][port]);
2448 		RZG2L_PCTRL_REG_ACCESS16(suspend, pctrl->base + PM(off), cache->pm[port]);
2449 		RZG2L_PCTRL_REG_ACCESS8(suspend, pctrl->base + P(off), cache->p[port]);
2453 						 cache->ien[0][port]);
2456 							 cache->ien[1][port]);
2468 	 * port offset are close together.
2484 			/* Gather caps of all port pins. */
2529 	/* Restore port registers. */
2530 	for (u32 port = 0; port < nports; port++) {
2538 		cfg = pctrl->data->port_pin_configs[port];
2548 			if (!(cache->pmc[port] & BIT(pin)))
2561 			pfc |= (cache->pfc[port] & (PFC_MASK << (pin * 4)));
2672 	.oen_max_port = 7, /* P7_1 is the maximum OEN port. */