Lines Matching refs:RCAR_GP_PIN
1241 RCAR_GP_PIN(1, 22),
1248 RCAR_GP_PIN(1, 21),
1257 RCAR_GP_PIN(7, 4),
1264 RCAR_GP_PIN(7, 10),
1271 RCAR_GP_PIN(7, 5),
1278 RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14),
1288 RCAR_GP_PIN(7, 16), RCAR_GP_PIN(7, 15),
1289 RCAR_GP_PIN(7, 11), RCAR_GP_PIN(7, 7),
1290 RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 3),
1291 RCAR_GP_PIN(7, 20), RCAR_GP_PIN(7, 19),
1292 RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17),
1293 RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 8),
1305 RCAR_GP_PIN(7, 9),
1312 RCAR_GP_PIN(7, 0),
1319 RCAR_GP_PIN(7, 1),
1326 RCAR_GP_PIN(7, 2),
1335 RCAR_GP_PIN(6, 4),
1342 RCAR_GP_PIN(6, 1),
1349 RCAR_GP_PIN(6, 3),
1356 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 0),
1366 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
1367 RCAR_GP_PIN(6, 13), RCAR_GP_PIN(6, 12),
1368 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 18),
1369 RCAR_GP_PIN(6, 9), RCAR_GP_PIN(6, 8),
1370 RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 14),
1371 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 19),
1383 RCAR_GP_PIN(6, 20),
1390 RCAR_GP_PIN(6, 10),
1397 RCAR_GP_PIN(6, 11),
1404 RCAR_GP_PIN(6, 5),
1413 RCAR_GP_PIN(5, 3),
1420 RCAR_GP_PIN(5, 5),
1427 RCAR_GP_PIN(5, 4),
1434 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 10),
1444 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 16),
1445 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 12),
1446 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 8),
1447 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 18),
1448 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 14),
1449 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 9),
1461 RCAR_GP_PIN(5, 7),
1468 RCAR_GP_PIN(5, 0),
1475 RCAR_GP_PIN(5, 1),
1482 RCAR_GP_PIN(5, 2),
1491 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1500 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1509 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1518 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1527 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
1536 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
1545 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
1554 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
1563 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
1572 RCAR_GP_PIN(2, 9),
1581 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12),
1588 RCAR_GP_PIN(1, 15),
1595 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1604 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
1611 RCAR_GP_PIN(0, 18),
1618 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
1627 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
1634 RCAR_GP_PIN(1, 10),
1641 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
1650 RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
1657 RCAR_GP_PIN(8, 13),
1664 RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 12),
1673 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 28),
1680 RCAR_GP_PIN(1, 25),
1687 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 27),
1696 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0),
1703 RCAR_GP_PIN(1, 3),
1710 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
1719 RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 0),
1728 RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 2),
1737 RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 4),
1746 RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 6),
1755 RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 8),
1764 RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 10),
1773 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
1774 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 5),
1775 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6),
1776 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
1786 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 10),
1793 RCAR_GP_PIN(3, 11),
1800 RCAR_GP_PIN(3, 12),
1807 RCAR_GP_PIN(3, 4),
1816 RCAR_GP_PIN(1, 10),
1823 RCAR_GP_PIN(1, 8),
1830 RCAR_GP_PIN(1, 7),
1837 RCAR_GP_PIN(1, 6),
1844 RCAR_GP_PIN(1, 9),
1851 RCAR_GP_PIN(1, 11),
1860 RCAR_GP_PIN(1, 3),
1867 RCAR_GP_PIN(1, 2),
1874 RCAR_GP_PIN(1, 1),
1881 RCAR_GP_PIN(1, 0),
1888 RCAR_GP_PIN(1, 4),
1895 RCAR_GP_PIN(1, 5),
1904 RCAR_GP_PIN(0, 17),
1911 RCAR_GP_PIN(0, 15),
1918 RCAR_GP_PIN(0, 14),
1925 RCAR_GP_PIN(0, 13),
1932 RCAR_GP_PIN(0, 16),
1939 RCAR_GP_PIN(0, 18),
1948 RCAR_GP_PIN(0, 3),
1955 RCAR_GP_PIN(0, 6),
1962 RCAR_GP_PIN(0, 1),
1969 RCAR_GP_PIN(0, 2),
1976 RCAR_GP_PIN(0, 4),
1983 RCAR_GP_PIN(0, 5),
1992 RCAR_GP_PIN(1, 25),
1999 RCAR_GP_PIN(1, 28),
2006 RCAR_GP_PIN(1, 23),
2013 RCAR_GP_PIN(1, 24),
2020 RCAR_GP_PIN(1, 26),
2027 RCAR_GP_PIN(1, 27),
2036 RCAR_GP_PIN(0, 11),
2043 RCAR_GP_PIN(0, 9),
2050 RCAR_GP_PIN(0, 8),
2057 RCAR_GP_PIN(0, 7),
2064 RCAR_GP_PIN(0, 10),
2071 RCAR_GP_PIN(0, 12),
2080 RCAR_GP_PIN(4, 21),
2089 RCAR_GP_PIN(4, 22),
2099 RCAR_GP_PIN(1, 15),
2108 RCAR_GP_PIN(3, 13),
2117 RCAR_GP_PIN(2, 13),
2126 RCAR_GP_PIN(2, 14),
2135 RCAR_GP_PIN(1, 22),
2144 RCAR_GP_PIN(2, 15),
2153 RCAR_GP_PIN(2, 16),
2162 RCAR_GP_PIN(2, 17),
2171 RCAR_GP_PIN(2, 18),
2180 RCAR_GP_PIN(2, 19),
2189 RCAR_GP_PIN(1, 13),
2198 RCAR_GP_PIN(1, 14),
2207 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 15),
2214 RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
2215 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
2225 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 25),
2232 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 23),
2233 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 26),
2243 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 12),
2250 RCAR_GP_PIN(1, 15),
2257 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2266 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2273 RCAR_GP_PIN(0, 18),
2280 RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
2289 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
2296 RCAR_GP_PIN(1, 10),
2303 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
2312 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2319 RCAR_GP_PIN(1, 4),
2326 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
2335 RCAR_GP_PIN(1, 27), RCAR_GP_PIN(1, 28),
2342 RCAR_GP_PIN(1, 24),
2349 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2358 RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 12),
2365 RCAR_GP_PIN(8, 8),
2372 RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 9),
2381 RCAR_GP_PIN(1, 17),
2389 RCAR_GP_PIN(8, 11),
2398 RCAR_GP_PIN(1, 20),
2405 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
2414 RCAR_GP_PIN(2, 8),
2421 RCAR_GP_PIN(2, 7),
2428 RCAR_GP_PIN(2, 12),
2435 RCAR_GP_PIN(2, 13),
2444 RCAR_GP_PIN(1, 25),
2451 RCAR_GP_PIN(1, 26),
2458 RCAR_GP_PIN(2, 0),
2465 RCAR_GP_PIN(2, 1),
2474 RCAR_GP_PIN(4, 4),
2481 RCAR_GP_PIN(4, 3),
2488 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
2498 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 12),
2499 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14),
2500 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
2501 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 11),
2502 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 13),
2503 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
2515 RCAR_GP_PIN(4, 20),
2522 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 2),
2529 RCAR_GP_PIN(4, 6),
2536 RCAR_GP_PIN(4, 5),
3711 { RCAR_GP_PIN(0, 7), 28, 3 }, /* MSIOF5_SS2 */
3712 { RCAR_GP_PIN(0, 6), 24, 3 }, /* IRQ0 */
3713 { RCAR_GP_PIN(0, 5), 20, 3 }, /* IRQ1 */
3714 { RCAR_GP_PIN(0, 4), 16, 3 }, /* IRQ2 */
3715 { RCAR_GP_PIN(0, 3), 12, 3 }, /* IRQ3 */
3716 { RCAR_GP_PIN(0, 2), 8, 3 }, /* GP0_02 */
3717 { RCAR_GP_PIN(0, 1), 4, 3 }, /* GP0_01 */
3718 { RCAR_GP_PIN(0, 0), 0, 3 }, /* GP0_00 */
3721 { RCAR_GP_PIN(0, 15), 28, 3 }, /* MSIOF2_SYNC */
3722 { RCAR_GP_PIN(0, 14), 24, 3 }, /* MSIOF2_SS1 */
3723 { RCAR_GP_PIN(0, 13), 20, 3 }, /* MSIOF2_SS2 */
3724 { RCAR_GP_PIN(0, 12), 16, 3 }, /* MSIOF5_RXD */
3725 { RCAR_GP_PIN(0, 11), 12, 3 }, /* MSIOF5_SCK */
3726 { RCAR_GP_PIN(0, 10), 8, 3 }, /* MSIOF5_TXD */
3727 { RCAR_GP_PIN(0, 9), 4, 3 }, /* MSIOF5_SYNC */
3728 { RCAR_GP_PIN(0, 8), 0, 3 }, /* MSIOF5_SS1 */
3731 { RCAR_GP_PIN(0, 18), 8, 3 }, /* MSIOF2_RXD */
3732 { RCAR_GP_PIN(0, 17), 4, 3 }, /* MSIOF2_SCK */
3733 { RCAR_GP_PIN(0, 16), 0, 3 }, /* MSIOF2_TXD */
3736 { RCAR_GP_PIN(1, 7), 28, 3 }, /* MSIOF0_SS1 */
3737 { RCAR_GP_PIN(1, 6), 24, 3 }, /* MSIOF0_SS2 */
3738 { RCAR_GP_PIN(1, 5), 20, 3 }, /* MSIOF1_RXD */
3739 { RCAR_GP_PIN(1, 4), 16, 3 }, /* MSIOF1_TXD */
3740 { RCAR_GP_PIN(1, 3), 12, 3 }, /* MSIOF1_SCK */
3741 { RCAR_GP_PIN(1, 2), 8, 3 }, /* MSIOF1_SYNC */
3742 { RCAR_GP_PIN(1, 1), 4, 3 }, /* MSIOF1_SS1 */
3743 { RCAR_GP_PIN(1, 0), 0, 3 }, /* MSIOF1_SS2 */
3746 { RCAR_GP_PIN(1, 15), 28, 3 }, /* HSCK0 */
3747 { RCAR_GP_PIN(1, 14), 24, 3 }, /* HRTS0_N */
3748 { RCAR_GP_PIN(1, 13), 20, 3 }, /* HCTS0_N */
3749 { RCAR_GP_PIN(1, 12), 16, 3 }, /* HTX0 */
3750 { RCAR_GP_PIN(1, 11), 12, 3 }, /* MSIOF0_RXD */
3751 { RCAR_GP_PIN(1, 10), 8, 3 }, /* MSIOF0_SCK */
3752 { RCAR_GP_PIN(1, 9), 4, 3 }, /* MSIOF0_TXD */
3753 { RCAR_GP_PIN(1, 8), 0, 3 }, /* MSIOF0_SYNC */
3756 { RCAR_GP_PIN(1, 23), 28, 3 }, /* GP1_23 */
3757 { RCAR_GP_PIN(1, 22), 24, 3 }, /* AUDIO_CLKIN */
3758 { RCAR_GP_PIN(1, 21), 20, 3 }, /* AUDIO_CLKOUT */
3759 { RCAR_GP_PIN(1, 20), 16, 3 }, /* SSI_SD */
3760 { RCAR_GP_PIN(1, 19), 12, 3 }, /* SSI_WS */
3761 { RCAR_GP_PIN(1, 18), 8, 3 }, /* SSI_SCK */
3762 { RCAR_GP_PIN(1, 17), 4, 3 }, /* SCIF_CLK */
3763 { RCAR_GP_PIN(1, 16), 0, 3 }, /* HRX0 */
3766 { RCAR_GP_PIN(1, 28), 16, 3 }, /* HTX3 */
3767 { RCAR_GP_PIN(1, 27), 12, 3 }, /* HCTS3_N */
3768 { RCAR_GP_PIN(1, 26), 8, 3 }, /* HRTS3_N */
3769 { RCAR_GP_PIN(1, 25), 4, 3 }, /* HSCK3 */
3770 { RCAR_GP_PIN(1, 24), 0, 3 }, /* HRX3 */
3773 { RCAR_GP_PIN(2, 7), 28, 3 }, /* TPU0TO1 */
3774 { RCAR_GP_PIN(2, 6), 24, 3 }, /* FXR_TXDB */
3775 { RCAR_GP_PIN(2, 5), 20, 3 }, /* FXR_TXENB_N */
3776 { RCAR_GP_PIN(2, 4), 16, 3 }, /* RXDB_EXTFXR */
3777 { RCAR_GP_PIN(2, 3), 12, 3 }, /* CLK_EXTFXR */
3778 { RCAR_GP_PIN(2, 2), 8, 3 }, /* RXDA_EXTFXR */
3779 { RCAR_GP_PIN(2, 1), 4, 3 }, /* FXR_TXENA_N */
3780 { RCAR_GP_PIN(2, 0), 0, 3 }, /* FXR_TXDA */
3783 { RCAR_GP_PIN(2, 15), 28, 3 }, /* CANFD3_RX */
3784 { RCAR_GP_PIN(2, 14), 24, 3 }, /* CANFD3_TX */
3785 { RCAR_GP_PIN(2, 13), 20, 3 }, /* CANFD2_RX */
3786 { RCAR_GP_PIN(2, 12), 16, 3 }, /* CANFD2_TX */
3787 { RCAR_GP_PIN(2, 11), 12, 3 }, /* CANFD0_RX */
3788 { RCAR_GP_PIN(2, 10), 8, 3 }, /* CANFD0_TX */
3789 { RCAR_GP_PIN(2, 9), 4, 3 }, /* CAN_CLK */
3790 { RCAR_GP_PIN(2, 8), 0, 3 }, /* TPU0TO0 */
3793 { RCAR_GP_PIN(2, 19), 12, 3 }, /* CANFD7_RX */
3794 { RCAR_GP_PIN(2, 18), 8, 3 }, /* CANFD7_TX */
3795 { RCAR_GP_PIN(2, 17), 4, 3 }, /* CANFD4_RX */
3796 { RCAR_GP_PIN(2, 16), 0, 3 }, /* CANFD4_TX */
3799 { RCAR_GP_PIN(3, 7), 28, 3 }, /* MMC_D4 */
3800 { RCAR_GP_PIN(3, 6), 24, 3 }, /* MMC_D5 */
3801 { RCAR_GP_PIN(3, 5), 20, 3 }, /* MMC_SD_D3 */
3802 { RCAR_GP_PIN(3, 4), 16, 3 }, /* MMC_DS */
3803 { RCAR_GP_PIN(3, 3), 12, 3 }, /* MMC_SD_CLK */
3804 { RCAR_GP_PIN(3, 2), 8, 3 }, /* MMC_SD_D2 */
3805 { RCAR_GP_PIN(3, 1), 4, 3 }, /* MMC_SD_D0 */
3806 { RCAR_GP_PIN(3, 0), 0, 3 }, /* MMC_SD_D1 */
3809 { RCAR_GP_PIN(3, 15), 28, 2 }, /* QSPI0_SSL */
3810 { RCAR_GP_PIN(3, 14), 24, 2 }, /* IPC_CLKOUT */
3811 { RCAR_GP_PIN(3, 13), 20, 2 }, /* IPC_CLKIN */
3812 { RCAR_GP_PIN(3, 12), 16, 3 }, /* SD_WP */
3813 { RCAR_GP_PIN(3, 11), 12, 3 }, /* SD_CD */
3814 { RCAR_GP_PIN(3, 10), 8, 3 }, /* MMC_SD_CMD */
3815 { RCAR_GP_PIN(3, 9), 4, 3 }, /* MMC_D6*/
3816 { RCAR_GP_PIN(3, 8), 0, 3 }, /* MMC_D7 */
3819 { RCAR_GP_PIN(3, 23), 28, 2 }, /* QSPI1_MISO_IO1 */
3820 { RCAR_GP_PIN(3, 22), 24, 2 }, /* QSPI1_SPCLK */
3821 { RCAR_GP_PIN(3, 21), 20, 2 }, /* QSPI1_MOSI_IO0 */
3822 { RCAR_GP_PIN(3, 20), 16, 2 }, /* QSPI0_SPCLK */
3823 { RCAR_GP_PIN(3, 19), 12, 2 }, /* QSPI0_MOSI_IO0 */
3824 { RCAR_GP_PIN(3, 18), 8, 2 }, /* QSPI0_MISO_IO1 */
3825 { RCAR_GP_PIN(3, 17), 4, 2 }, /* QSPI0_IO2 */
3826 { RCAR_GP_PIN(3, 16), 0, 2 }, /* QSPI0_IO3 */
3829 { RCAR_GP_PIN(3, 29), 20, 2 }, /* RPC_INT_N */
3830 { RCAR_GP_PIN(3, 28), 16, 2 }, /* RPC_WP_N */
3831 { RCAR_GP_PIN(3, 27), 12, 2 }, /* RPC_RESET_N */
3832 { RCAR_GP_PIN(3, 26), 8, 2 }, /* QSPI1_IO3 */
3833 { RCAR_GP_PIN(3, 25), 4, 2 }, /* QSPI1_SSL */
3834 { RCAR_GP_PIN(3, 24), 0, 2 }, /* QSPI1_IO2 */
3837 { RCAR_GP_PIN(4, 7), 28, 3 }, /* TSN0_RX_CTL */
3838 { RCAR_GP_PIN(4, 6), 24, 3 }, /* TSN0_AVTP_CAPTURE */
3839 { RCAR_GP_PIN(4, 5), 20, 3 }, /* TSN0_AVTP_MATCH */
3840 { RCAR_GP_PIN(4, 4), 16, 3 }, /* TSN0_LINK */
3841 { RCAR_GP_PIN(4, 3), 12, 3 }, /* TSN0_PHY_INT */
3842 { RCAR_GP_PIN(4, 2), 8, 3 }, /* TSN0_AVTP_PPS1 */
3843 { RCAR_GP_PIN(4, 1), 4, 3 }, /* TSN0_MDC */
3844 { RCAR_GP_PIN(4, 0), 0, 3 }, /* TSN0_MDIO */
3847 { RCAR_GP_PIN(4, 15), 28, 3 }, /* TSN0_TD0 */
3848 { RCAR_GP_PIN(4, 14), 24, 3 }, /* TSN0_TD1 */
3849 { RCAR_GP_PIN(4, 13), 20, 3 }, /* TSN0_RD1 */
3850 { RCAR_GP_PIN(4, 12), 16, 3 }, /* TSN0_TXC */
3851 { RCAR_GP_PIN(4, 11), 12, 3 }, /* TSN0_RXC */
3852 { RCAR_GP_PIN(4, 10), 8, 3 }, /* TSN0_RD0 */
3853 { RCAR_GP_PIN(4, 9), 4, 3 }, /* TSN0_TX_CTL */
3854 { RCAR_GP_PIN(4, 8), 0, 3 }, /* TSN0_AVTP_PPS0 */
3857 { RCAR_GP_PIN(4, 23), 28, 3 }, /* AVS0 */
3858 { RCAR_GP_PIN(4, 22), 24, 3 }, /* PCIE1_CLKREQ_N */
3859 { RCAR_GP_PIN(4, 21), 20, 3 }, /* PCIE0_CLKREQ_N */
3860 { RCAR_GP_PIN(4, 20), 16, 3 }, /* TSN0_TXCREFCLK */
3861 { RCAR_GP_PIN(4, 19), 12, 3 }, /* TSN0_TD2 */
3862 { RCAR_GP_PIN(4, 18), 8, 3 }, /* TSN0_TD3 */
3863 { RCAR_GP_PIN(4, 17), 4, 3 }, /* TSN0_RD2 */
3864 { RCAR_GP_PIN(4, 16), 0, 3 }, /* TSN0_RD3 */
3867 { RCAR_GP_PIN(4, 24), 0, 3 }, /* AVS1 */
3870 { RCAR_GP_PIN(5, 7), 28, 3 }, /* AVB2_TXCREFCLK */
3871 { RCAR_GP_PIN(5, 6), 24, 3 }, /* AVB2_MDC */
3872 { RCAR_GP_PIN(5, 5), 20, 3 }, /* AVB2_MAGIC */
3873 { RCAR_GP_PIN(5, 4), 16, 3 }, /* AVB2_PHY_INT */
3874 { RCAR_GP_PIN(5, 3), 12, 3 }, /* AVB2_LINK */
3875 { RCAR_GP_PIN(5, 2), 8, 3 }, /* AVB2_AVTP_MATCH */
3876 { RCAR_GP_PIN(5, 1), 4, 3 }, /* AVB2_AVTP_CAPTURE */
3877 { RCAR_GP_PIN(5, 0), 0, 3 }, /* AVB2_AVTP_PPS */
3880 { RCAR_GP_PIN(5, 15), 28, 3 }, /* AVB2_TD0 */
3881 { RCAR_GP_PIN(5, 14), 24, 3 }, /* AVB2_RD1 */
3882 { RCAR_GP_PIN(5, 13), 20, 3 }, /* AVB2_RD2 */
3883 { RCAR_GP_PIN(5, 12), 16, 3 }, /* AVB2_TD1 */
3884 { RCAR_GP_PIN(5, 11), 12, 3 }, /* AVB2_TD2 */
3885 { RCAR_GP_PIN(5, 10), 8, 3 }, /* AVB2_MDIO */
3886 { RCAR_GP_PIN(5, 9), 4, 3 }, /* AVB2_RD3 */
3887 { RCAR_GP_PIN(5, 8), 0, 3 }, /* AVB2_TD3 */
3890 { RCAR_GP_PIN(5, 20), 16, 3 }, /* AVB2_RX_CTL */
3891 { RCAR_GP_PIN(5, 19), 12, 3 }, /* AVB2_TX_CTL */
3892 { RCAR_GP_PIN(5, 18), 8, 3 }, /* AVB2_RXC */
3893 { RCAR_GP_PIN(5, 17), 4, 3 }, /* AVB2_RD0 */
3894 { RCAR_GP_PIN(5, 16), 0, 3 }, /* AVB2_TXC */
3897 { RCAR_GP_PIN(6, 7), 28, 3 }, /* AVB1_TX_CTL */
3898 { RCAR_GP_PIN(6, 6), 24, 3 }, /* AVB1_TXC */
3899 { RCAR_GP_PIN(6, 5), 20, 3 }, /* AVB1_AVTP_MATCH */
3900 { RCAR_GP_PIN(6, 4), 16, 3 }, /* AVB1_LINK */
3901 { RCAR_GP_PIN(6, 3), 12, 3 }, /* AVB1_PHY_INT */
3902 { RCAR_GP_PIN(6, 2), 8, 3 }, /* AVB1_MDC */
3903 { RCAR_GP_PIN(6, 1), 4, 3 }, /* AVB1_MAGIC */
3904 { RCAR_GP_PIN(6, 0), 0, 3 }, /* AVB1_MDIO */
3907 { RCAR_GP_PIN(6, 15), 28, 3 }, /* AVB1_RD0 */
3908 { RCAR_GP_PIN(6, 14), 24, 3 }, /* AVB1_RD1 */
3909 { RCAR_GP_PIN(6, 13), 20, 3 }, /* AVB1_TD0 */
3910 { RCAR_GP_PIN(6, 12), 16, 3 }, /* AVB1_TD1 */
3911 { RCAR_GP_PIN(6, 11), 12, 3 }, /* AVB1_AVTP_CAPTURE */
3912 { RCAR_GP_PIN(6, 10), 8, 3 }, /* AVB1_AVTP_PPS */
3913 { RCAR_GP_PIN(6, 9), 4, 3 }, /* AVB1_RX_CTL */
3914 { RCAR_GP_PIN(6, 8), 0, 3 }, /* AVB1_RXC */
3917 { RCAR_GP_PIN(6, 20), 16, 3 }, /* AVB1_TXCREFCLK */
3918 { RCAR_GP_PIN(6, 19), 12, 3 }, /* AVB1_RD3 */
3919 { RCAR_GP_PIN(6, 18), 8, 3 }, /* AVB1_TD3 */
3920 { RCAR_GP_PIN(6, 17), 4, 3 }, /* AVB1_RD2 */
3921 { RCAR_GP_PIN(6, 16), 0, 3 }, /* AVB1_TD2 */
3924 { RCAR_GP_PIN(7, 7), 28, 3 }, /* AVB0_TD1 */
3925 { RCAR_GP_PIN(7, 6), 24, 3 }, /* AVB0_TD2 */
3926 { RCAR_GP_PIN(7, 5), 20, 3 }, /* AVB0_PHY_INT */
3927 { RCAR_GP_PIN(7, 4), 16, 3 }, /* AVB0_LINK */
3928 { RCAR_GP_PIN(7, 3), 12, 3 }, /* AVB0_TD3 */
3929 { RCAR_GP_PIN(7, 2), 8, 3 }, /* AVB0_AVTP_MATCH */
3930 { RCAR_GP_PIN(7, 1), 4, 3 }, /* AVB0_AVTP_CAPTURE */
3931 { RCAR_GP_PIN(7, 0), 0, 3 }, /* AVB0_AVTP_PPS */
3934 { RCAR_GP_PIN(7, 15), 28, 3 }, /* AVB0_TXC */
3935 { RCAR_GP_PIN(7, 14), 24, 3 }, /* AVB0_MDIO */
3936 { RCAR_GP_PIN(7, 13), 20, 3 }, /* AVB0_MDC */
3937 { RCAR_GP_PIN(7, 12), 16, 3 }, /* AVB0_RD2 */
3938 { RCAR_GP_PIN(7, 11), 12, 3 }, /* AVB0_TD0 */
3939 { RCAR_GP_PIN(7, 10), 8, 3 }, /* AVB0_MAGIC */
3940 { RCAR_GP_PIN(7, 9), 4, 3 }, /* AVB0_TXCREFCLK */
3941 { RCAR_GP_PIN(7, 8), 0, 3 }, /* AVB0_RD3 */
3944 { RCAR_GP_PIN(7, 20), 16, 3 }, /* AVB0_RX_CTL */
3945 { RCAR_GP_PIN(7, 19), 12, 3 }, /* AVB0_RXC */
3946 { RCAR_GP_PIN(7, 18), 8, 3 }, /* AVB0_RD0 */
3947 { RCAR_GP_PIN(7, 17), 4, 3 }, /* AVB0_RD1 */
3948 { RCAR_GP_PIN(7, 16), 0, 3 }, /* AVB0_TX_CTL */
3951 { RCAR_GP_PIN(8, 7), 28, 3 }, /* SDA3 */
3952 { RCAR_GP_PIN(8, 6), 24, 3 }, /* SCL3 */
3953 { RCAR_GP_PIN(8, 5), 20, 3 }, /* SDA2 */
3954 { RCAR_GP_PIN(8, 4), 16, 3 }, /* SCL2 */
3955 { RCAR_GP_PIN(8, 3), 12, 3 }, /* SDA1 */
3956 { RCAR_GP_PIN(8, 2), 8, 3 }, /* SCL1 */
3957 { RCAR_GP_PIN(8, 1), 4, 3 }, /* SDA0 */
3958 { RCAR_GP_PIN(8, 0), 0, 3 }, /* SCL0 */
3961 { RCAR_GP_PIN(8, 13), 20, 3 }, /* GP8_13 */
3962 { RCAR_GP_PIN(8, 12), 16, 3 }, /* GP8_12 */
3963 { RCAR_GP_PIN(8, 11), 12, 3 }, /* SDA5 */
3964 { RCAR_GP_PIN(8, 10), 8, 3 }, /* SCL5 */
3965 { RCAR_GP_PIN(8, 9), 4, 3 }, /* SDA4 */
3966 { RCAR_GP_PIN(8, 8), 0, 3 }, /* SCL4 */
3999 case RCAR_GP_PIN(0, 0) ... RCAR_GP_PIN(0, 18):
4003 case RCAR_GP_PIN(1, 0) ... RCAR_GP_PIN(1, 22):
4007 case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 12):
4027 case RCAR_GP_PIN(8, 0) ... RCAR_GP_PIN(8, 13):
4038 [ 0] = RCAR_GP_PIN(0, 0), /* GP0_00 */
4039 [ 1] = RCAR_GP_PIN(0, 1), /* GP0_01 */
4040 [ 2] = RCAR_GP_PIN(0, 2), /* GP0_02 */
4041 [ 3] = RCAR_GP_PIN(0, 3), /* IRQ3 */
4042 [ 4] = RCAR_GP_PIN(0, 4), /* IRQ2 */
4043 [ 5] = RCAR_GP_PIN(0, 5), /* IRQ1 */
4044 [ 6] = RCAR_GP_PIN(0, 6), /* IRQ0 */
4045 [ 7] = RCAR_GP_PIN(0, 7), /* MSIOF5_SS2 */
4046 [ 8] = RCAR_GP_PIN(0, 8), /* MSIOF5_SS1 */
4047 [ 9] = RCAR_GP_PIN(0, 9), /* MSIOF5_SYNC */
4048 [10] = RCAR_GP_PIN(0, 10), /* MSIOF5_TXD */
4049 [11] = RCAR_GP_PIN(0, 11), /* MSIOF5_SCK */
4050 [12] = RCAR_GP_PIN(0, 12), /* MSIOF5_RXD */
4051 [13] = RCAR_GP_PIN(0, 13), /* MSIOF2_SS2 */
4052 [14] = RCAR_GP_PIN(0, 14), /* MSIOF2_SS1 */
4053 [15] = RCAR_GP_PIN(0, 15), /* MSIOF2_SYNC */
4054 [16] = RCAR_GP_PIN(0, 16), /* MSIOF2_TXD */
4055 [17] = RCAR_GP_PIN(0, 17), /* MSIOF2_SCK */
4056 [18] = RCAR_GP_PIN(0, 18), /* MSIOF2_RXD */
4072 [ 0] = RCAR_GP_PIN(1, 0), /* MSIOF1_SS2 */
4073 [ 1] = RCAR_GP_PIN(1, 1), /* MSIOF1_SS1 */
4074 [ 2] = RCAR_GP_PIN(1, 2), /* MSIOF1_SYNC */
4075 [ 3] = RCAR_GP_PIN(1, 3), /* MSIOF1_SCK */
4076 [ 4] = RCAR_GP_PIN(1, 4), /* MSIOF1_TXD */
4077 [ 5] = RCAR_GP_PIN(1, 5), /* MSIOF1_RXD */
4078 [ 6] = RCAR_GP_PIN(1, 6), /* MSIOF0_SS2 */
4079 [ 7] = RCAR_GP_PIN(1, 7), /* MSIOF0_SS1 */
4080 [ 8] = RCAR_GP_PIN(1, 8), /* MSIOF0_SYNC */
4081 [ 9] = RCAR_GP_PIN(1, 9), /* MSIOF0_TXD */
4082 [10] = RCAR_GP_PIN(1, 10), /* MSIOF0_SCK */
4083 [11] = RCAR_GP_PIN(1, 11), /* MSIOF0_RXD */
4084 [12] = RCAR_GP_PIN(1, 12), /* HTX0 */
4085 [13] = RCAR_GP_PIN(1, 13), /* HCTS0_N */
4086 [14] = RCAR_GP_PIN(1, 14), /* HRTS0_N */
4087 [15] = RCAR_GP_PIN(1, 15), /* HSCK0 */
4088 [16] = RCAR_GP_PIN(1, 16), /* HRX0 */
4089 [17] = RCAR_GP_PIN(1, 17), /* SCIF_CLK */
4090 [18] = RCAR_GP_PIN(1, 18), /* SSI_SCK */
4091 [19] = RCAR_GP_PIN(1, 19), /* SSI_WS */
4092 [20] = RCAR_GP_PIN(1, 20), /* SSI_SD */
4093 [21] = RCAR_GP_PIN(1, 21), /* AUDIO_CLKOUT */
4094 [22] = RCAR_GP_PIN(1, 22), /* AUDIO_CLKIN */
4095 [23] = RCAR_GP_PIN(1, 23), /* GP1_23 */
4096 [24] = RCAR_GP_PIN(1, 24), /* HRX3 */
4097 [25] = RCAR_GP_PIN(1, 25), /* HSCK3 */
4098 [26] = RCAR_GP_PIN(1, 26), /* HRTS3_N */
4099 [27] = RCAR_GP_PIN(1, 27), /* HCTS3_N */
4100 [28] = RCAR_GP_PIN(1, 28), /* HTX3 */
4106 [ 0] = RCAR_GP_PIN(2, 0), /* FXR_TXDA */
4107 [ 1] = RCAR_GP_PIN(2, 1), /* FXR_TXENA_N */
4108 [ 2] = RCAR_GP_PIN(2, 2), /* RXDA_EXTFXR */
4109 [ 3] = RCAR_GP_PIN(2, 3), /* CLK_EXTFXR */
4110 [ 4] = RCAR_GP_PIN(2, 4), /* RXDB_EXTFXR */
4111 [ 5] = RCAR_GP_PIN(2, 5), /* FXR_TXENB_N */
4112 [ 6] = RCAR_GP_PIN(2, 6), /* FXR_TXDB */
4113 [ 7] = RCAR_GP_PIN(2, 7), /* TPU0TO1 */
4114 [ 8] = RCAR_GP_PIN(2, 8), /* TPU0TO0 */
4115 [ 9] = RCAR_GP_PIN(2, 9), /* CAN_CLK */
4116 [10] = RCAR_GP_PIN(2, 10), /* CANFD0_TX */
4117 [11] = RCAR_GP_PIN(2, 11), /* CANFD0_RX */
4118 [12] = RCAR_GP_PIN(2, 12), /* CANFD2_TX */
4119 [13] = RCAR_GP_PIN(2, 13), /* CANFD2_RX */
4120 [14] = RCAR_GP_PIN(2, 14), /* CANFD3_TX */
4121 [15] = RCAR_GP_PIN(2, 15), /* CANFD3_RX */
4122 [16] = RCAR_GP_PIN(2, 16), /* CANFD4_TX */
4123 [17] = RCAR_GP_PIN(2, 17), /* CANFD4_RX */
4124 [18] = RCAR_GP_PIN(2, 18), /* CANFD7_TX */
4125 [19] = RCAR_GP_PIN(2, 19), /* CANFD7_RX */
4140 [ 0] = RCAR_GP_PIN(3, 0), /* MMC_SD_D1 */
4141 [ 1] = RCAR_GP_PIN(3, 1), /* MMC_SD_D0 */
4142 [ 2] = RCAR_GP_PIN(3, 2), /* MMC_SD_D2 */
4143 [ 3] = RCAR_GP_PIN(3, 3), /* MMC_SD_CLK */
4144 [ 4] = RCAR_GP_PIN(3, 4), /* MMC_DS */
4145 [ 5] = RCAR_GP_PIN(3, 5), /* MMC_SD_D3 */
4146 [ 6] = RCAR_GP_PIN(3, 6), /* MMC_D5 */
4147 [ 7] = RCAR_GP_PIN(3, 7), /* MMC_D4 */
4148 [ 8] = RCAR_GP_PIN(3, 8), /* MMC_D7 */
4149 [ 9] = RCAR_GP_PIN(3, 9), /* MMC_D6 */
4150 [10] = RCAR_GP_PIN(3, 10), /* MMC_SD_CMD */
4151 [11] = RCAR_GP_PIN(3, 11), /* SD_CD */
4152 [12] = RCAR_GP_PIN(3, 12), /* SD_WP */
4153 [13] = RCAR_GP_PIN(3, 13), /* IPC_CLKIN */
4154 [14] = RCAR_GP_PIN(3, 14), /* IPC_CLKOUT */
4155 [15] = RCAR_GP_PIN(3, 15), /* QSPI0_SSL */
4156 [16] = RCAR_GP_PIN(3, 16), /* QSPI0_IO3 */
4157 [17] = RCAR_GP_PIN(3, 17), /* QSPI0_IO2 */
4158 [18] = RCAR_GP_PIN(3, 18), /* QSPI0_MISO_IO1 */
4159 [19] = RCAR_GP_PIN(3, 19), /* QSPI0_MOSI_IO0 */
4160 [20] = RCAR_GP_PIN(3, 20), /* QSPI0_SPCLK */
4161 [21] = RCAR_GP_PIN(3, 21), /* QSPI1_MOSI_IO0 */
4162 [22] = RCAR_GP_PIN(3, 22), /* QSPI1_SPCLK */
4163 [23] = RCAR_GP_PIN(3, 23), /* QSPI1_MISO_IO1 */
4164 [24] = RCAR_GP_PIN(3, 24), /* QSPI1_IO2 */
4165 [25] = RCAR_GP_PIN(3, 25), /* QSPI1_SSL */
4166 [26] = RCAR_GP_PIN(3, 26), /* QSPI1_IO3 */
4167 [27] = RCAR_GP_PIN(3, 27), /* RPC_RESET_N */
4168 [28] = RCAR_GP_PIN(3, 28), /* RPC_WP_N */
4169 [29] = RCAR_GP_PIN(3, 29), /* RPC_INT_N */
4174 [ 0] = RCAR_GP_PIN(4, 0), /* TSN0_MDIO */
4175 [ 1] = RCAR_GP_PIN(4, 1), /* TSN0_MDC */
4176 [ 2] = RCAR_GP_PIN(4, 2), /* TSN0_AVTP_PPS1 */
4177 [ 3] = RCAR_GP_PIN(4, 3), /* TSN0_PHY_INT */
4178 [ 4] = RCAR_GP_PIN(4, 4), /* TSN0_LINK */
4179 [ 5] = RCAR_GP_PIN(4, 5), /* TSN0_AVTP_MATCH */
4180 [ 6] = RCAR_GP_PIN(4, 6), /* TSN0_AVTP_CAPTURE */
4181 [ 7] = RCAR_GP_PIN(4, 7), /* TSN0_RX_CTL */
4182 [ 8] = RCAR_GP_PIN(4, 8), /* TSN0_AVTP_PPS0 */
4183 [ 9] = RCAR_GP_PIN(4, 9), /* TSN0_TX_CTL */
4184 [10] = RCAR_GP_PIN(4, 10), /* TSN0_RD0 */
4185 [11] = RCAR_GP_PIN(4, 11), /* TSN0_RXC */
4186 [12] = RCAR_GP_PIN(4, 12), /* TSN0_TXC */
4187 [13] = RCAR_GP_PIN(4, 13), /* TSN0_RD1 */
4188 [14] = RCAR_GP_PIN(4, 14), /* TSN0_TD1 */
4189 [15] = RCAR_GP_PIN(4, 15), /* TSN0_TD0 */
4190 [16] = RCAR_GP_PIN(4, 16), /* TSN0_RD3 */
4191 [17] = RCAR_GP_PIN(4, 17), /* TSN0_RD2 */
4192 [18] = RCAR_GP_PIN(4, 18), /* TSN0_TD3 */
4193 [19] = RCAR_GP_PIN(4, 19), /* TSN0_TD2 */
4194 [20] = RCAR_GP_PIN(4, 20), /* TSN0_TXCREFCLK */
4195 [21] = RCAR_GP_PIN(4, 21), /* PCIE0_CLKREQ_N */
4196 [22] = RCAR_GP_PIN(4, 22), /* PCIE1_CLKREQ_N */
4197 [23] = RCAR_GP_PIN(4, 23), /* AVS0 */
4198 [24] = RCAR_GP_PIN(4, 24), /* AVS1 */
4208 [ 0] = RCAR_GP_PIN(5, 0), /* AVB2_AVTP_PPS */
4209 [ 1] = RCAR_GP_PIN(5, 1), /* AVB0_AVTP_CAPTURE */
4210 [ 2] = RCAR_GP_PIN(5, 2), /* AVB2_AVTP_MATCH */
4211 [ 3] = RCAR_GP_PIN(5, 3), /* AVB2_LINK */
4212 [ 4] = RCAR_GP_PIN(5, 4), /* AVB2_PHY_INT */
4213 [ 5] = RCAR_GP_PIN(5, 5), /* AVB2_MAGIC */
4214 [ 6] = RCAR_GP_PIN(5, 6), /* AVB2_MDC */
4215 [ 7] = RCAR_GP_PIN(5, 7), /* AVB2_TXCREFCLK */
4216 [ 8] = RCAR_GP_PIN(5, 8), /* AVB2_TD3 */
4217 [ 9] = RCAR_GP_PIN(5, 9), /* AVB2_RD3 */
4218 [10] = RCAR_GP_PIN(5, 10), /* AVB2_MDIO */
4219 [11] = RCAR_GP_PIN(5, 11), /* AVB2_TD2 */
4220 [12] = RCAR_GP_PIN(5, 12), /* AVB2_TD1 */
4221 [13] = RCAR_GP_PIN(5, 13), /* AVB2_RD2 */
4222 [14] = RCAR_GP_PIN(5, 14), /* AVB2_RD1 */
4223 [15] = RCAR_GP_PIN(5, 15), /* AVB2_TD0 */
4224 [16] = RCAR_GP_PIN(5, 16), /* AVB2_TXC */
4225 [17] = RCAR_GP_PIN(5, 17), /* AVB2_RD0 */
4226 [18] = RCAR_GP_PIN(5, 18), /* AVB2_RXC */
4227 [19] = RCAR_GP_PIN(5, 19), /* AVB2_TX_CTL */
4228 [20] = RCAR_GP_PIN(5, 20), /* AVB2_RX_CTL */
4242 [ 0] = RCAR_GP_PIN(6, 0), /* AVB1_MDIO */
4243 [ 1] = RCAR_GP_PIN(6, 1), /* AVB1_MAGIC */
4244 [ 2] = RCAR_GP_PIN(6, 2), /* AVB1_MDC */
4245 [ 3] = RCAR_GP_PIN(6, 3), /* AVB1_PHY_INT */
4246 [ 4] = RCAR_GP_PIN(6, 4), /* AVB1_LINK */
4247 [ 5] = RCAR_GP_PIN(6, 5), /* AVB1_AVTP_MATCH */
4248 [ 6] = RCAR_GP_PIN(6, 6), /* AVB1_TXC */
4249 [ 7] = RCAR_GP_PIN(6, 7), /* AVB1_TX_CTL */
4250 [ 8] = RCAR_GP_PIN(6, 8), /* AVB1_RXC */
4251 [ 9] = RCAR_GP_PIN(6, 9), /* AVB1_RX_CTL */
4252 [10] = RCAR_GP_PIN(6, 10), /* AVB1_AVTP_PPS */
4253 [11] = RCAR_GP_PIN(6, 11), /* AVB1_AVTP_CAPTURE */
4254 [12] = RCAR_GP_PIN(6, 12), /* AVB1_TD1 */
4255 [13] = RCAR_GP_PIN(6, 13), /* AVB1_TD0 */
4256 [14] = RCAR_GP_PIN(6, 14), /* AVB1_RD1*/
4257 [15] = RCAR_GP_PIN(6, 15), /* AVB1_RD0 */
4258 [16] = RCAR_GP_PIN(6, 16), /* AVB1_TD2 */
4259 [17] = RCAR_GP_PIN(6, 17), /* AVB1_RD2 */
4260 [18] = RCAR_GP_PIN(6, 18), /* AVB1_TD3 */
4261 [19] = RCAR_GP_PIN(6, 19), /* AVB1_RD3 */
4262 [20] = RCAR_GP_PIN(6, 20), /* AVB1_TXCREFCLK */
4276 [ 0] = RCAR_GP_PIN(7, 0), /* AVB0_AVTP_PPS */
4277 [ 1] = RCAR_GP_PIN(7, 1), /* AVB0_AVTP_CAPTURE */
4278 [ 2] = RCAR_GP_PIN(7, 2), /* AVB0_AVTP_MATCH */
4279 [ 3] = RCAR_GP_PIN(7, 3), /* AVB0_TD3 */
4280 [ 4] = RCAR_GP_PIN(7, 4), /* AVB0_LINK */
4281 [ 5] = RCAR_GP_PIN(7, 5), /* AVB0_PHY_INT */
4282 [ 6] = RCAR_GP_PIN(7, 6), /* AVB0_TD2 */
4283 [ 7] = RCAR_GP_PIN(7, 7), /* AVB0_TD1 */
4284 [ 8] = RCAR_GP_PIN(7, 8), /* AVB0_RD3 */
4285 [ 9] = RCAR_GP_PIN(7, 9), /* AVB0_TXCREFCLK */
4286 [10] = RCAR_GP_PIN(7, 10), /* AVB0_MAGIC */
4287 [11] = RCAR_GP_PIN(7, 11), /* AVB0_TD0 */
4288 [12] = RCAR_GP_PIN(7, 12), /* AVB0_RD2 */
4289 [13] = RCAR_GP_PIN(7, 13), /* AVB0_MDC */
4290 [14] = RCAR_GP_PIN(7, 14), /* AVB0_MDIO */
4291 [15] = RCAR_GP_PIN(7, 15), /* AVB0_TXC */
4292 [16] = RCAR_GP_PIN(7, 16), /* AVB0_TX_CTL */
4293 [17] = RCAR_GP_PIN(7, 17), /* AVB0_RD1 */
4294 [18] = RCAR_GP_PIN(7, 18), /* AVB0_RD0 */
4295 [19] = RCAR_GP_PIN(7, 19), /* AVB0_RXC */
4296 [20] = RCAR_GP_PIN(7, 20), /* AVB0_RX_CTL */
4310 [ 0] = RCAR_GP_PIN(8, 0), /* SCL0 */
4311 [ 1] = RCAR_GP_PIN(8, 1), /* SDA0 */
4312 [ 2] = RCAR_GP_PIN(8, 2), /* SCL1 */
4313 [ 3] = RCAR_GP_PIN(8, 3), /* SDA1 */
4314 [ 4] = RCAR_GP_PIN(8, 4), /* SCL2 */
4315 [ 5] = RCAR_GP_PIN(8, 5), /* SDA2 */
4316 [ 6] = RCAR_GP_PIN(8, 6), /* SCL3 */
4317 [ 7] = RCAR_GP_PIN(8, 7), /* SDA3 */
4318 [ 8] = RCAR_GP_PIN(8, 8), /* SCL4 */
4319 [ 9] = RCAR_GP_PIN(8, 9), /* SDA4 */
4320 [10] = RCAR_GP_PIN(8, 10), /* SCL5 */
4321 [11] = RCAR_GP_PIN(8, 11), /* SDA5 */
4322 [12] = RCAR_GP_PIN(8, 12), /* GP8_12 */
4323 [13] = RCAR_GP_PIN(8, 13), /* GP8_13 */