Lines Matching refs:RCAR_GP_PIN
1245 RCAR_GP_PIN(4, 17),
1252 RCAR_GP_PIN(4, 15),
1259 RCAR_GP_PIN(4, 16),
1266 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
1276 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1277 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1278 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1279 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
1280 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
1281 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1291 RCAR_GP_PIN(4, 12),
1298 RCAR_GP_PIN(4, 20),
1305 RCAR_GP_PIN(4, 19),
1312 RCAR_GP_PIN(4, 18),
1321 RCAR_GP_PIN(5, 17),
1328 RCAR_GP_PIN(5, 15),
1335 RCAR_GP_PIN(5, 16),
1342 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 13),
1352 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1353 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1354 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1355 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
1356 RCAR_GP_PIN(5, 2), RCAR_GP_PIN(5, 3),
1357 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1367 RCAR_GP_PIN(5, 12),
1374 RCAR_GP_PIN(5, 20),
1381 RCAR_GP_PIN(5, 19),
1388 RCAR_GP_PIN(5, 18),
1397 RCAR_GP_PIN(6, 17),
1404 RCAR_GP_PIN(6, 15),
1411 RCAR_GP_PIN(6, 16),
1418 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 13),
1428 RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
1429 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1430 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
1431 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
1432 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
1433 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
1443 RCAR_GP_PIN(6, 12),
1450 RCAR_GP_PIN(6, 20),
1457 RCAR_GP_PIN(6, 19),
1464 RCAR_GP_PIN(6, 18),
1473 RCAR_GP_PIN(7, 17),
1480 RCAR_GP_PIN(7, 15),
1487 RCAR_GP_PIN(7, 16),
1494 RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 13),
1504 RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7),
1505 RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
1506 RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 11),
1507 RCAR_GP_PIN(7, 0), RCAR_GP_PIN(7, 1),
1508 RCAR_GP_PIN(7, 2), RCAR_GP_PIN(7, 3),
1509 RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5),
1519 RCAR_GP_PIN(7, 12),
1526 RCAR_GP_PIN(7, 20),
1533 RCAR_GP_PIN(7, 19),
1540 RCAR_GP_PIN(7, 18),
1549 RCAR_GP_PIN(8, 17),
1556 RCAR_GP_PIN(8, 15),
1563 RCAR_GP_PIN(8, 16),
1570 RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 13),
1580 RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7),
1581 RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
1582 RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 11),
1583 RCAR_GP_PIN(8, 0), RCAR_GP_PIN(8, 1),
1584 RCAR_GP_PIN(8, 2), RCAR_GP_PIN(8, 3),
1585 RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5),
1595 RCAR_GP_PIN(8, 12),
1602 RCAR_GP_PIN(8, 20),
1609 RCAR_GP_PIN(8, 19),
1616 RCAR_GP_PIN(8, 18),
1625 RCAR_GP_PIN(9, 17),
1632 RCAR_GP_PIN(9, 15),
1639 RCAR_GP_PIN(9, 16),
1646 RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 13),
1656 RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7),
1657 RCAR_GP_PIN(9, 8), RCAR_GP_PIN(9, 9),
1658 RCAR_GP_PIN(9, 10), RCAR_GP_PIN(9, 11),
1659 RCAR_GP_PIN(9, 0), RCAR_GP_PIN(9, 1),
1660 RCAR_GP_PIN(9, 2), RCAR_GP_PIN(9, 3),
1661 RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5),
1671 RCAR_GP_PIN(9, 12),
1678 RCAR_GP_PIN(9, 20),
1685 RCAR_GP_PIN(9, 19),
1692 RCAR_GP_PIN(9, 18),
1701 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
1710 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
1719 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
1728 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
1737 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
1746 RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
1755 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
1764 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
1773 RCAR_GP_PIN(3, 0),
1782 RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
1783 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
1784 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15),
1785 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12),
1786 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
1787 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1799 RCAR_GP_PIN(1, 24),
1806 RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 26),
1813 RCAR_GP_PIN(1, 27),
1822 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 5),
1829 RCAR_GP_PIN(1, 2),
1836 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
1845 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
1852 RCAR_GP_PIN(1, 18),
1859 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19),
1868 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1875 RCAR_GP_PIN(2, 5),
1882 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6),
1891 RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 17),
1898 RCAR_GP_PIN(1, 14),
1905 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
1914 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
1923 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
1932 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6),
1941 RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 8),
1950 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1959 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 12),
1968 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14),
1977 RCAR_GP_PIN(1, 24),
1984 RCAR_GP_PIN(1, 25),
1991 RCAR_GP_PIN(1, 26),
1998 RCAR_GP_PIN(1, 27),
2005 RCAR_GP_PIN(2, 14),
2012 RCAR_GP_PIN(2, 15),
2021 RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20),
2022 RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22),
2023 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2024 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 27),
2034 RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 18),
2041 RCAR_GP_PIN(0, 16),
2048 RCAR_GP_PIN(0, 15),
2055 RCAR_GP_PIN(0, 17),
2064 RCAR_GP_PIN(1, 8),
2071 RCAR_GP_PIN(1, 9),
2078 RCAR_GP_PIN(1, 10),
2085 RCAR_GP_PIN(1, 11),
2092 RCAR_GP_PIN(1, 7),
2099 RCAR_GP_PIN(1, 6),
2108 RCAR_GP_PIN(1, 14),
2115 RCAR_GP_PIN(1, 15),
2122 RCAR_GP_PIN(1, 16),
2129 RCAR_GP_PIN(1, 17),
2136 RCAR_GP_PIN(1, 13),
2143 RCAR_GP_PIN(1, 12),
2152 RCAR_GP_PIN(1, 20),
2159 RCAR_GP_PIN(1, 21),
2166 RCAR_GP_PIN(1, 22),
2173 RCAR_GP_PIN(1, 23),
2180 RCAR_GP_PIN(1, 19),
2187 RCAR_GP_PIN(1, 18),
2196 RCAR_GP_PIN(2, 20),
2203 RCAR_GP_PIN(2, 21),
2210 RCAR_GP_PIN(2, 16),
2217 RCAR_GP_PIN(2, 17),
2224 RCAR_GP_PIN(2, 19),
2231 RCAR_GP_PIN(2, 18),
2240 RCAR_GP_PIN(2, 6),
2247 RCAR_GP_PIN(2, 7),
2254 RCAR_GP_PIN(2, 8),
2261 RCAR_GP_PIN(2, 9),
2268 RCAR_GP_PIN(2, 5),
2275 RCAR_GP_PIN(2, 4),
2284 RCAR_GP_PIN(2, 12),
2291 RCAR_GP_PIN(2, 13),
2298 RCAR_GP_PIN(2, 14),
2305 RCAR_GP_PIN(2, 15),
2312 RCAR_GP_PIN(2, 11),
2319 RCAR_GP_PIN(2, 10),
2328 RCAR_GP_PIN(3, 5),
2337 RCAR_GP_PIN(3, 6),
2346 RCAR_GP_PIN(3, 7),
2355 RCAR_GP_PIN(3, 8),
2364 RCAR_GP_PIN(3, 9),
2373 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 5),
2380 RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
2381 RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
2391 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 11),
2398 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
2399 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
2409 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 5),
2416 RCAR_GP_PIN(1, 2),
2423 RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
2432 RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
2439 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 1),
2446 RCAR_GP_PIN(1, 18),
2453 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19),
2462 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2469 RCAR_GP_PIN(1, 13),
2476 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2485 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
2492 RCAR_GP_PIN(2, 5),
2499 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6),
2508 RCAR_GP_PIN(1, 0),
2517 RCAR_GP_PIN(2, 23),
2524 RCAR_GP_PIN(1, 23),
2532 RCAR_GP_PIN(2, 24),
2539 RCAR_GP_PIN(2, 10),
2547 RCAR_GP_PIN(2, 11),
2555 RCAR_GP_PIN(2, 12),
2564 RCAR_GP_PIN(2, 21),
2571 RCAR_GP_PIN(2, 22),
2578 RCAR_GP_PIN(3, 5),
2585 RCAR_GP_PIN(3, 6),
3638 { RCAR_GP_PIN(0, 7), 28, 2 }, /* QSPI1_MOSI_IO0 */
3639 { RCAR_GP_PIN(0, 6), 24, 2 }, /* QSPI1_SPCLK */
3640 { RCAR_GP_PIN(0, 5), 20, 2 }, /* QSPI0_SSL */
3641 { RCAR_GP_PIN(0, 4), 16, 2 }, /* QSPI0_IO3 */
3642 { RCAR_GP_PIN(0, 3), 12, 2 }, /* QSPI0_IO2 */
3643 { RCAR_GP_PIN(0, 2), 8, 2 }, /* QSPI0_MISO_IO1 */
3644 { RCAR_GP_PIN(0, 1), 4, 2 }, /* QSPI0_MOSI_IO0 */
3645 { RCAR_GP_PIN(0, 0), 0, 2 }, /* QSPI0_SPCLK */
3648 { RCAR_GP_PIN(0, 15), 28, 3 }, /* SD_WP */
3649 { RCAR_GP_PIN(0, 14), 24, 2 }, /* RPC_INT_N */
3650 { RCAR_GP_PIN(0, 13), 20, 2 }, /* RPC_WP_N */
3651 { RCAR_GP_PIN(0, 12), 16, 2 }, /* RPC_RESET_N */
3652 { RCAR_GP_PIN(0, 11), 12, 2 }, /* QSPI1_SSL */
3653 { RCAR_GP_PIN(0, 10), 8, 2 }, /* QSPI1_IO3 */
3654 { RCAR_GP_PIN(0, 9), 4, 2 }, /* QSPI1_IO2 */
3655 { RCAR_GP_PIN(0, 8), 0, 2 }, /* QSPI1_MISO_IO1 */
3658 { RCAR_GP_PIN(0, 23), 28, 3 }, /* MMC_SD_CLK */
3659 { RCAR_GP_PIN(0, 22), 24, 3 }, /* MMC_SD_D3 */
3660 { RCAR_GP_PIN(0, 21), 20, 3 }, /* MMC_SD_D2 */
3661 { RCAR_GP_PIN(0, 20), 16, 3 }, /* MMC_SD_D1 */
3662 { RCAR_GP_PIN(0, 19), 12, 3 }, /* MMC_SD_D0 */
3663 { RCAR_GP_PIN(0, 18), 8, 3 }, /* MMC_SD_CMD */
3664 { RCAR_GP_PIN(0, 17), 4, 3 }, /* MMC_DS */
3665 { RCAR_GP_PIN(0, 16), 0, 3 }, /* SD_CD */
3668 { RCAR_GP_PIN(0, 27), 12, 3 }, /* MMC_D7 */
3669 { RCAR_GP_PIN(0, 26), 8, 3 }, /* MMC_D6 */
3670 { RCAR_GP_PIN(0, 25), 4, 3 }, /* MMC_D5 */
3671 { RCAR_GP_PIN(0, 24), 0, 3 }, /* MMC_D4 */
3674 { RCAR_GP_PIN(1, 7), 28, 3 }, /* MSIOF0_TXD */
3675 { RCAR_GP_PIN(1, 6), 24, 3 }, /* MSIOF0_RXD */
3676 { RCAR_GP_PIN(1, 5), 20, 3 }, /* HTX0 */
3677 { RCAR_GP_PIN(1, 4), 16, 3 }, /* HCTS0_N */
3678 { RCAR_GP_PIN(1, 3), 12, 3 }, /* HRTS0_N */
3679 { RCAR_GP_PIN(1, 2), 8, 3 }, /* HSCK0 */
3680 { RCAR_GP_PIN(1, 1), 4, 3 }, /* HRX0 */
3681 { RCAR_GP_PIN(1, 0), 0, 3 }, /* SCIF_CLK */
3684 { RCAR_GP_PIN(1, 15), 28, 3 }, /* MSIOF1_SYNC */
3685 { RCAR_GP_PIN(1, 14), 24, 3 }, /* MSIOF1_SCK */
3686 { RCAR_GP_PIN(1, 13), 20, 3 }, /* MSIOF1_TXD */
3687 { RCAR_GP_PIN(1, 12), 16, 3 }, /* MSIOF1_RXD */
3688 { RCAR_GP_PIN(1, 11), 12, 3 }, /* MSIOF0_SS2 */
3689 { RCAR_GP_PIN(1, 10), 8, 3 }, /* MSIOF0_SS1 */
3690 { RCAR_GP_PIN(1, 9), 4, 3 }, /* MSIOF0_SYNC */
3691 { RCAR_GP_PIN(1, 8), 0, 3 }, /* MSIOF0_SCK */
3694 { RCAR_GP_PIN(1, 23), 28, 3 }, /* MSIOF2_SS2 */
3695 { RCAR_GP_PIN(1, 22), 24, 3 }, /* MSIOF2_SS1 */
3696 { RCAR_GP_PIN(1, 21), 20, 3 }, /* MSIOF2_SYNC */
3697 { RCAR_GP_PIN(1, 20), 16, 3 }, /* MSIOF2_SCK */
3698 { RCAR_GP_PIN(1, 19), 12, 3 }, /* MSIOF2_TXD */
3699 { RCAR_GP_PIN(1, 18), 8, 3 }, /* MSIOF2_RXD */
3700 { RCAR_GP_PIN(1, 17), 4, 3 }, /* MSIOF1_SS2 */
3701 { RCAR_GP_PIN(1, 16), 0, 3 }, /* MSIOF1_SS1 */
3704 { RCAR_GP_PIN(1, 30), 24, 3 }, /* GP1_30 */
3705 { RCAR_GP_PIN(1, 29), 20, 3 }, /* GP1_29 */
3706 { RCAR_GP_PIN(1, 28), 16, 3 }, /* GP1_28 */
3707 { RCAR_GP_PIN(1, 27), 12, 3 }, /* IRQ3 */
3708 { RCAR_GP_PIN(1, 26), 8, 3 }, /* IRQ2 */
3709 { RCAR_GP_PIN(1, 25), 4, 3 }, /* IRQ1 */
3710 { RCAR_GP_PIN(1, 24), 0, 3 }, /* IRQ0 */
3713 { RCAR_GP_PIN(2, 7), 28, 3 }, /* GP2_07 */
3714 { RCAR_GP_PIN(2, 6), 24, 3 }, /* GP2_06 */
3715 { RCAR_GP_PIN(2, 5), 20, 3 }, /* GP2_05 */
3716 { RCAR_GP_PIN(2, 4), 16, 3 }, /* GP2_04 */
3717 { RCAR_GP_PIN(2, 3), 12, 3 }, /* GP2_03 */
3718 { RCAR_GP_PIN(2, 2), 8, 3 }, /* GP2_02 */
3719 { RCAR_GP_PIN(2, 1), 4, 2 }, /* IPC_CLKOUT */
3720 { RCAR_GP_PIN(2, 0), 0, 2 }, /* IPC_CLKIN */
3723 { RCAR_GP_PIN(2, 15), 28, 3 }, /* GP2_15 */
3724 { RCAR_GP_PIN(2, 14), 24, 3 }, /* GP2_14 */
3725 { RCAR_GP_PIN(2, 13), 20, 3 }, /* GP2_13 */
3726 { RCAR_GP_PIN(2, 12), 16, 3 }, /* GP2_12 */
3727 { RCAR_GP_PIN(2, 11), 12, 3 }, /* GP2_11 */
3728 { RCAR_GP_PIN(2, 10), 8, 3 }, /* GP2_10 */
3729 { RCAR_GP_PIN(2, 9), 4, 3 }, /* GP2_9 */
3730 { RCAR_GP_PIN(2, 8), 0, 3 }, /* GP2_8 */
3733 { RCAR_GP_PIN(2, 23), 28, 3 }, /* TCLK1_A */
3734 { RCAR_GP_PIN(2, 22), 24, 3 }, /* TPU0TO1 */
3735 { RCAR_GP_PIN(2, 21), 20, 3 }, /* TPU0TO0 */
3736 { RCAR_GP_PIN(2, 20), 16, 3 }, /* CLK_EXTFXR */
3737 { RCAR_GP_PIN(2, 19), 12, 3 }, /* RXDB_EXTFXR */
3738 { RCAR_GP_PIN(2, 18), 8, 3 }, /* FXR_TXDB */
3739 { RCAR_GP_PIN(2, 17), 4, 3 }, /* RXDA_EXTFXR_A */
3740 { RCAR_GP_PIN(2, 16), 0, 3 }, /* FXR_TXDA_A */
3743 { RCAR_GP_PIN(2, 24), 0, 3 }, /* TCLK2_A */
3746 { RCAR_GP_PIN(3, 7), 28, 3 }, /* CANFD3_TX */
3747 { RCAR_GP_PIN(3, 6), 24, 3 }, /* CANFD2_RX */
3748 { RCAR_GP_PIN(3, 5), 20, 3 }, /* CANFD2_TX */
3749 { RCAR_GP_PIN(3, 4), 16, 3 }, /* CANFD1_RX */
3750 { RCAR_GP_PIN(3, 3), 12, 3 }, /* CANFD1_TX */
3751 { RCAR_GP_PIN(3, 2), 8, 3 }, /* CANFD0_RX */
3752 { RCAR_GP_PIN(3, 1), 4, 2 }, /* CANFD0_TX */
3753 { RCAR_GP_PIN(3, 0), 0, 2 }, /* CAN_CLK */
3756 { RCAR_GP_PIN(3, 15), 28, 3 }, /* CANFD7_TX */
3757 { RCAR_GP_PIN(3, 14), 24, 3 }, /* CANFD6_RX */
3758 { RCAR_GP_PIN(3, 13), 20, 3 }, /* CANFD6_TX */
3759 { RCAR_GP_PIN(3, 12), 16, 3 }, /* CANFD5_RX */
3760 { RCAR_GP_PIN(3, 11), 12, 3 }, /* CANFD5_TX */
3761 { RCAR_GP_PIN(3, 10), 8, 3 }, /* CANFD4_RX */
3762 { RCAR_GP_PIN(3, 9), 4, 3 }, /* CANFD4_TX */
3763 { RCAR_GP_PIN(3, 8), 0, 3 }, /* CANFD3_RX */
3766 { RCAR_GP_PIN(3, 16), 0, 3 }, /* CANFD7_RX */
3769 { RCAR_GP_PIN(4, 7), 28, 3 }, /* AVB0_TXC */
3770 { RCAR_GP_PIN(4, 6), 24, 3 }, /* AVB0_TX_CTL */
3771 { RCAR_GP_PIN(4, 5), 20, 3 }, /* AVB0_RD3 */
3772 { RCAR_GP_PIN(4, 4), 16, 3 }, /* AVB0_RD2 */
3773 { RCAR_GP_PIN(4, 3), 12, 3 }, /* AVB0_RD1 */
3774 { RCAR_GP_PIN(4, 2), 8, 3 }, /* AVB0_RD0 */
3775 { RCAR_GP_PIN(4, 1), 4, 3 }, /* AVB0_RXC */
3776 { RCAR_GP_PIN(4, 0), 0, 3 }, /* AVB0_RX_CTL */
3779 { RCAR_GP_PIN(4, 15), 28, 3 }, /* AVB0_MAGIC */
3780 { RCAR_GP_PIN(4, 14), 24, 3 }, /* AVB0_MDC */
3781 { RCAR_GP_PIN(4, 13), 20, 3 }, /* AVB0_MDIO */
3782 { RCAR_GP_PIN(4, 12), 16, 3 }, /* AVB0_TXCREFCLK */
3783 { RCAR_GP_PIN(4, 11), 12, 3 }, /* AVB0_TD3 */
3784 { RCAR_GP_PIN(4, 10), 8, 3 }, /* AVB0_TD2 */
3785 { RCAR_GP_PIN(4, 9), 4, 3 }, /* AVB0_TD1*/
3786 { RCAR_GP_PIN(4, 8), 0, 3 }, /* AVB0_TD0 */
3789 { RCAR_GP_PIN(4, 23), 28, 3 }, /* PCIE2_CLKREQ_N */
3790 { RCAR_GP_PIN(4, 22), 24, 3 }, /* PCIE1_CLKREQ_N */
3791 { RCAR_GP_PIN(4, 21), 20, 3 }, /* PCIE0_CLKREQ_N */
3792 { RCAR_GP_PIN(4, 20), 16, 3 }, /* AVB0_AVTP_PPS */
3793 { RCAR_GP_PIN(4, 19), 12, 3 }, /* AVB0_AVTP_CAPTURE */
3794 { RCAR_GP_PIN(4, 18), 8, 3 }, /* AVB0_AVTP_MATCH */
3795 { RCAR_GP_PIN(4, 17), 4, 3 }, /* AVB0_LINK */
3796 { RCAR_GP_PIN(4, 16), 0, 3 }, /* AVB0_PHY_INT */
3799 { RCAR_GP_PIN(4, 26), 8, 3 }, /* AVS1 */
3800 { RCAR_GP_PIN(4, 25), 4, 3 }, /* AVS0 */
3801 { RCAR_GP_PIN(4, 24), 0, 3 }, /* PCIE3_CLKREQ_N */
3804 { RCAR_GP_PIN(5, 7), 28, 3 }, /* AVB1_TXC */
3805 { RCAR_GP_PIN(5, 6), 24, 3 }, /* AVB1_TX_CTL */
3806 { RCAR_GP_PIN(5, 5), 20, 3 }, /* AVB1_RD3 */
3807 { RCAR_GP_PIN(5, 4), 16, 3 }, /* AVB1_RD2 */
3808 { RCAR_GP_PIN(5, 3), 12, 3 }, /* AVB1_RD1 */
3809 { RCAR_GP_PIN(5, 2), 8, 3 }, /* AVB1_RD0 */
3810 { RCAR_GP_PIN(5, 1), 4, 3 }, /* AVB1_RXC */
3811 { RCAR_GP_PIN(5, 0), 0, 3 }, /* AVB1_RX_CTL */
3814 { RCAR_GP_PIN(5, 15), 28, 3 }, /* AVB1_MAGIC */
3815 { RCAR_GP_PIN(5, 14), 24, 3 }, /* AVB1_MDC */
3816 { RCAR_GP_PIN(5, 13), 20, 3 }, /* AVB1_MDIO */
3817 { RCAR_GP_PIN(5, 12), 16, 3 }, /* AVB1_TXCREFCLK */
3818 { RCAR_GP_PIN(5, 11), 12, 3 }, /* AVB1_TD3 */
3819 { RCAR_GP_PIN(5, 10), 8, 3 }, /* AVB1_TD2 */
3820 { RCAR_GP_PIN(5, 9), 4, 3 }, /* AVB1_TD1*/
3821 { RCAR_GP_PIN(5, 8), 0, 3 }, /* AVB1_TD0 */
3824 { RCAR_GP_PIN(5, 20), 16, 3 }, /* AVB1_AVTP_PPS */
3825 { RCAR_GP_PIN(5, 19), 12, 3 }, /* AVB1_AVTP_CAPTURE */
3826 { RCAR_GP_PIN(5, 18), 8, 3 }, /* AVB1_AVTP_MATCH */
3827 { RCAR_GP_PIN(5, 17), 4, 3 }, /* AVB1_LINK */
3828 { RCAR_GP_PIN(5, 16), 0, 3 }, /* AVB1_PHY_INT */
3831 { RCAR_GP_PIN(6, 7), 28, 3 }, /* AVB2_TXC */
3832 { RCAR_GP_PIN(6, 6), 24, 3 }, /* AVB2_TX_CTL */
3833 { RCAR_GP_PIN(6, 5), 20, 3 }, /* AVB2_RD3 */
3834 { RCAR_GP_PIN(6, 4), 16, 3 }, /* AVB2_RD2 */
3835 { RCAR_GP_PIN(6, 3), 12, 3 }, /* AVB2_RD1 */
3836 { RCAR_GP_PIN(6, 2), 8, 3 }, /* AVB2_RD0 */
3837 { RCAR_GP_PIN(6, 1), 4, 3 }, /* AVB2_RXC */
3838 { RCAR_GP_PIN(6, 0), 0, 3 }, /* AVB2_RX_CTL */
3841 { RCAR_GP_PIN(6, 15), 28, 3 }, /* AVB2_MAGIC */
3842 { RCAR_GP_PIN(6, 14), 24, 3 }, /* AVB2_MDC */
3843 { RCAR_GP_PIN(6, 13), 20, 3 }, /* AVB2_MDIO */
3844 { RCAR_GP_PIN(6, 12), 16, 3 }, /* AVB2_TXCREFCLK */
3845 { RCAR_GP_PIN(6, 11), 12, 3 }, /* AVB2_TD3 */
3846 { RCAR_GP_PIN(6, 10), 8, 3 }, /* AVB2_TD2 */
3847 { RCAR_GP_PIN(6, 9), 4, 3 }, /* AVB2_TD1*/
3848 { RCAR_GP_PIN(6, 8), 0, 3 }, /* AVB2_TD0 */
3851 { RCAR_GP_PIN(6, 20), 16, 3 }, /* AVB2_AVTP_PPS */
3852 { RCAR_GP_PIN(6, 19), 12, 3 }, /* AVB2_AVTP_CAPTURE */
3853 { RCAR_GP_PIN(6, 18), 8, 3 }, /* AVB2_AVTP_MATCH */
3854 { RCAR_GP_PIN(6, 17), 4, 3 }, /* AVB2_LINK */
3855 { RCAR_GP_PIN(6, 16), 0, 3 }, /* AVB2_PHY_INT */
3858 { RCAR_GP_PIN(7, 7), 28, 3 }, /* AVB3_TXC */
3859 { RCAR_GP_PIN(7, 6), 24, 3 }, /* AVB3_TX_CTL */
3860 { RCAR_GP_PIN(7, 5), 20, 3 }, /* AVB3_RD3 */
3861 { RCAR_GP_PIN(7, 4), 16, 3 }, /* AVB3_RD2 */
3862 { RCAR_GP_PIN(7, 3), 12, 3 }, /* AVB3_RD1 */
3863 { RCAR_GP_PIN(7, 2), 8, 3 }, /* AVB3_RD0 */
3864 { RCAR_GP_PIN(7, 1), 4, 3 }, /* AVB3_RXC */
3865 { RCAR_GP_PIN(7, 0), 0, 3 }, /* AVB3_RX_CTL */
3868 { RCAR_GP_PIN(7, 15), 28, 3 }, /* AVB3_MAGIC */
3869 { RCAR_GP_PIN(7, 14), 24, 3 }, /* AVB3_MDC */
3870 { RCAR_GP_PIN(7, 13), 20, 3 }, /* AVB3_MDIO */
3871 { RCAR_GP_PIN(7, 12), 16, 3 }, /* AVB3_TXCREFCLK */
3872 { RCAR_GP_PIN(7, 11), 12, 3 }, /* AVB3_TD3 */
3873 { RCAR_GP_PIN(7, 10), 8, 3 }, /* AVB3_TD2 */
3874 { RCAR_GP_PIN(7, 9), 4, 3 }, /* AVB3_TD1*/
3875 { RCAR_GP_PIN(7, 8), 0, 3 }, /* AVB3_TD0 */
3878 { RCAR_GP_PIN(7, 20), 16, 3 }, /* AVB3_AVTP_PPS */
3879 { RCAR_GP_PIN(7, 19), 12, 3 }, /* AVB3_AVTP_CAPTURE */
3880 { RCAR_GP_PIN(7, 18), 8, 3 }, /* AVB3_AVTP_MATCH */
3881 { RCAR_GP_PIN(7, 17), 4, 3 }, /* AVB3_LINK */
3882 { RCAR_GP_PIN(7, 16), 0, 3 }, /* AVB3_PHY_INT */
3885 { RCAR_GP_PIN(8, 7), 28, 3 }, /* AVB4_TXC */
3886 { RCAR_GP_PIN(8, 6), 24, 3 }, /* AVB4_TX_CTL */
3887 { RCAR_GP_PIN(8, 5), 20, 3 }, /* AVB4_RD3 */
3888 { RCAR_GP_PIN(8, 4), 16, 3 }, /* AVB4_RD2 */
3889 { RCAR_GP_PIN(8, 3), 12, 3 }, /* AVB4_RD1 */
3890 { RCAR_GP_PIN(8, 2), 8, 3 }, /* AVB4_RD0 */
3891 { RCAR_GP_PIN(8, 1), 4, 3 }, /* AVB4_RXC */
3892 { RCAR_GP_PIN(8, 0), 0, 3 }, /* AVB4_RX_CTL */
3895 { RCAR_GP_PIN(8, 15), 28, 3 }, /* AVB4_MAGIC */
3896 { RCAR_GP_PIN(8, 14), 24, 3 }, /* AVB4_MDC */
3897 { RCAR_GP_PIN(8, 13), 20, 3 }, /* AVB4_MDIO */
3898 { RCAR_GP_PIN(8, 12), 16, 3 }, /* AVB4_TXCREFCLK */
3899 { RCAR_GP_PIN(8, 11), 12, 3 }, /* AVB4_TD3 */
3900 { RCAR_GP_PIN(8, 10), 8, 3 }, /* AVB4_TD2 */
3901 { RCAR_GP_PIN(8, 9), 4, 3 }, /* AVB4_TD1*/
3902 { RCAR_GP_PIN(8, 8), 0, 3 }, /* AVB4_TD0 */
3905 { RCAR_GP_PIN(8, 20), 16, 3 }, /* AVB4_AVTP_PPS */
3906 { RCAR_GP_PIN(8, 19), 12, 3 }, /* AVB4_AVTP_CAPTURE */
3907 { RCAR_GP_PIN(8, 18), 8, 3 }, /* AVB4_AVTP_MATCH */
3908 { RCAR_GP_PIN(8, 17), 4, 3 }, /* AVB4_LINK */
3909 { RCAR_GP_PIN(8, 16), 0, 3 }, /* AVB4_PHY_INT */
3912 { RCAR_GP_PIN(9, 7), 28, 3 }, /* AVB5_TXC */
3913 { RCAR_GP_PIN(9, 6), 24, 3 }, /* AVB5_TX_CTL */
3914 { RCAR_GP_PIN(9, 5), 20, 3 }, /* AVB5_RD3 */
3915 { RCAR_GP_PIN(9, 4), 16, 3 }, /* AVB5_RD2 */
3916 { RCAR_GP_PIN(9, 3), 12, 3 }, /* AVB5_RD1 */
3917 { RCAR_GP_PIN(9, 2), 8, 3 }, /* AVB5_RD0 */
3918 { RCAR_GP_PIN(9, 1), 4, 3 }, /* AVB5_RXC */
3919 { RCAR_GP_PIN(9, 0), 0, 3 }, /* AVB5_RX_CTL */
3922 { RCAR_GP_PIN(9, 15), 28, 3 }, /* AVB5_MAGIC */
3923 { RCAR_GP_PIN(9, 14), 24, 3 }, /* AVB5_MDC */
3924 { RCAR_GP_PIN(9, 13), 20, 3 }, /* AVB5_MDIO */
3925 { RCAR_GP_PIN(9, 12), 16, 3 }, /* AVB5_TXCREFCLK */
3926 { RCAR_GP_PIN(9, 11), 12, 3 }, /* AVB5_TD3 */
3927 { RCAR_GP_PIN(9, 10), 8, 3 }, /* AVB5_TD2 */
3928 { RCAR_GP_PIN(9, 9), 4, 3 }, /* AVB5_TD1*/
3929 { RCAR_GP_PIN(9, 8), 0, 3 }, /* AVB5_TD0 */
3932 { RCAR_GP_PIN(9, 20), 16, 3 }, /* AVB5_AVTP_PPS */
3933 { RCAR_GP_PIN(9, 19), 12, 3 }, /* AVB5_AVTP_CAPTURE */
3934 { RCAR_GP_PIN(9, 18), 8, 3 }, /* AVB5_AVTP_MATCH */
3935 { RCAR_GP_PIN(9, 17), 4, 3 }, /* AVB5_LINK */
3936 { RCAR_GP_PIN(9, 16), 0, 3 }, /* AVB5_PHY_INT */
3973 if (pin >= RCAR_GP_PIN(0, 15) && pin <= RCAR_GP_PIN(0, 27))
3977 if (pin >= RCAR_GP_PIN(1, 0) && pin <= RCAR_GP_PIN(1, 30))
3981 if (pin >= RCAR_GP_PIN(2, 2) && pin <= RCAR_GP_PIN(2, 15))
3985 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
3989 if (pin >= RCAR_GP_PIN(5, 0) && pin <= RCAR_GP_PIN(5, 17))
3993 if (pin >= RCAR_GP_PIN(6, 0) && pin <= RCAR_GP_PIN(6, 17))
3997 if (pin >= RCAR_GP_PIN(7, 0) && pin <= RCAR_GP_PIN(7, 17))
4001 if (pin >= RCAR_GP_PIN(8, 0) && pin <= RCAR_GP_PIN(8, 17))
4005 if (pin >= RCAR_GP_PIN(9, 0) && pin <= RCAR_GP_PIN(9, 17))
4013 [ 0] = RCAR_GP_PIN(0, 0), /* QSPI0_SPCLK */
4014 [ 1] = RCAR_GP_PIN(0, 1), /* QSPI0_MOSI_IO0 */
4015 [ 2] = RCAR_GP_PIN(0, 2), /* QSPI0_MISO_IO1 */
4016 [ 3] = RCAR_GP_PIN(0, 3), /* QSPI0_IO2 */
4017 [ 4] = RCAR_GP_PIN(0, 4), /* QSPI0_IO3 */
4018 [ 5] = RCAR_GP_PIN(0, 5), /* QSPI0_SSL */
4019 [ 6] = RCAR_GP_PIN(0, 6), /* QSPI1_SPCLK */
4020 [ 7] = RCAR_GP_PIN(0, 7), /* QSPI1_MOSI_IO0 */
4021 [ 8] = RCAR_GP_PIN(0, 8), /* QSPI1_MISO_IO1 */
4022 [ 9] = RCAR_GP_PIN(0, 9), /* QSPI1_IO2 */
4023 [10] = RCAR_GP_PIN(0, 10), /* QSPI1_IO3 */
4024 [11] = RCAR_GP_PIN(0, 11), /* QSPI1_SSL */
4025 [12] = RCAR_GP_PIN(0, 12), /* RPC_RESET_N */
4026 [13] = RCAR_GP_PIN(0, 13), /* RPC_WP_N */
4027 [14] = RCAR_GP_PIN(0, 14), /* RPC_INT_N */
4028 [15] = RCAR_GP_PIN(0, 15), /* SD_WP */
4029 [16] = RCAR_GP_PIN(0, 16), /* SD_CD */
4030 [17] = RCAR_GP_PIN(0, 17), /* MMC_DS */
4031 [18] = RCAR_GP_PIN(0, 18), /* MMC_SD_CMD */
4032 [19] = RCAR_GP_PIN(0, 19), /* MMC_SD_D0 */
4033 [20] = RCAR_GP_PIN(0, 20), /* MMC_SD_D1 */
4034 [21] = RCAR_GP_PIN(0, 21), /* MMC_SD_D2 */
4035 [22] = RCAR_GP_PIN(0, 22), /* MMC_SD_D3 */
4036 [23] = RCAR_GP_PIN(0, 23), /* MMC_SD_CLK */
4037 [24] = RCAR_GP_PIN(0, 24), /* MMC_D4 */
4038 [25] = RCAR_GP_PIN(0, 25), /* MMC_D5 */
4039 [26] = RCAR_GP_PIN(0, 26), /* MMC_D6 */
4040 [27] = RCAR_GP_PIN(0, 27), /* MMC_D7 */
4047 [ 0] = RCAR_GP_PIN(1, 0), /* SCIF_CLK */
4048 [ 1] = RCAR_GP_PIN(1, 1), /* HRX0 */
4049 [ 2] = RCAR_GP_PIN(1, 2), /* HSCK0 */
4050 [ 3] = RCAR_GP_PIN(1, 3), /* HRTS0_N */
4051 [ 4] = RCAR_GP_PIN(1, 4), /* HCTS0_N */
4052 [ 5] = RCAR_GP_PIN(1, 5), /* HTX0 */
4053 [ 6] = RCAR_GP_PIN(1, 6), /* MSIOF0_RXD */
4054 [ 7] = RCAR_GP_PIN(1, 7), /* MSIOF0_TXD */
4055 [ 8] = RCAR_GP_PIN(1, 8), /* MSIOF0_SCK */
4056 [ 9] = RCAR_GP_PIN(1, 9), /* MSIOF0_SYNC */
4057 [10] = RCAR_GP_PIN(1, 10), /* MSIOF0_SS1 */
4058 [11] = RCAR_GP_PIN(1, 11), /* MSIOF0_SS2 */
4059 [12] = RCAR_GP_PIN(1, 12), /* MSIOF1_RXD */
4060 [13] = RCAR_GP_PIN(1, 13), /* MSIOF1_TXD */
4061 [14] = RCAR_GP_PIN(1, 14), /* MSIOF1_SCK */
4062 [15] = RCAR_GP_PIN(1, 15), /* MSIOF1_SYNC */
4063 [16] = RCAR_GP_PIN(1, 16), /* MSIOF1_SS1 */
4064 [17] = RCAR_GP_PIN(1, 17), /* MSIOF1_SS2 */
4065 [18] = RCAR_GP_PIN(1, 18), /* MSIOF2_RXD */
4066 [19] = RCAR_GP_PIN(1, 19), /* MSIOF2_TXD */
4067 [20] = RCAR_GP_PIN(1, 20), /* MSIOF2_SCK */
4068 [21] = RCAR_GP_PIN(1, 21), /* MSIOF2_SYNC */
4069 [22] = RCAR_GP_PIN(1, 22), /* MSIOF2_SS1 */
4070 [23] = RCAR_GP_PIN(1, 23), /* MSIOF2_SS2 */
4071 [24] = RCAR_GP_PIN(1, 24), /* IRQ0 */
4072 [25] = RCAR_GP_PIN(1, 25), /* IRQ1 */
4073 [26] = RCAR_GP_PIN(1, 26), /* IRQ2 */
4074 [27] = RCAR_GP_PIN(1, 27), /* IRQ3 */
4075 [28] = RCAR_GP_PIN(1, 28), /* GP1_28 */
4076 [29] = RCAR_GP_PIN(1, 29), /* GP1_29 */
4077 [30] = RCAR_GP_PIN(1, 30), /* GP1_30 */
4081 [ 0] = RCAR_GP_PIN(2, 0), /* IPC_CLKIN */
4082 [ 1] = RCAR_GP_PIN(2, 1), /* IPC_CLKOUT */
4083 [ 2] = RCAR_GP_PIN(2, 2), /* GP2_02 */
4084 [ 3] = RCAR_GP_PIN(2, 3), /* GP2_03 */
4085 [ 4] = RCAR_GP_PIN(2, 4), /* GP2_04 */
4086 [ 5] = RCAR_GP_PIN(2, 5), /* GP2_05 */
4087 [ 6] = RCAR_GP_PIN(2, 6), /* GP2_06 */
4088 [ 7] = RCAR_GP_PIN(2, 7), /* GP2_07 */
4089 [ 8] = RCAR_GP_PIN(2, 8), /* GP2_08 */
4090 [ 9] = RCAR_GP_PIN(2, 9), /* GP2_09 */
4091 [10] = RCAR_GP_PIN(2, 10), /* GP2_10 */
4092 [11] = RCAR_GP_PIN(2, 11), /* GP2_11 */
4093 [12] = RCAR_GP_PIN(2, 12), /* GP2_12 */
4094 [13] = RCAR_GP_PIN(2, 13), /* GP2_13 */
4095 [14] = RCAR_GP_PIN(2, 14), /* GP2_14 */
4096 [15] = RCAR_GP_PIN(2, 15), /* GP2_15 */
4097 [16] = RCAR_GP_PIN(2, 16), /* FXR_TXDA_A */
4098 [17] = RCAR_GP_PIN(2, 17), /* RXDA_EXTFXR_A */
4099 [18] = RCAR_GP_PIN(2, 18), /* FXR_TXDB */
4100 [19] = RCAR_GP_PIN(2, 19), /* RXDB_EXTFXR */
4101 [20] = RCAR_GP_PIN(2, 20), /* CLK_EXTFXR */
4102 [21] = RCAR_GP_PIN(2, 21), /* TPU0TO0 */
4103 [22] = RCAR_GP_PIN(2, 22), /* TPU0TO1 */
4104 [23] = RCAR_GP_PIN(2, 23), /* TCLK1_A */
4105 [24] = RCAR_GP_PIN(2, 24), /* TCLK2_A */
4115 [ 0] = RCAR_GP_PIN(3, 0), /* CAN_CLK */
4116 [ 1] = RCAR_GP_PIN(3, 1), /* CANFD0_TX */
4117 [ 2] = RCAR_GP_PIN(3, 2), /* CANFD0_RX */
4118 [ 3] = RCAR_GP_PIN(3, 3), /* CANFD1_TX */
4119 [ 4] = RCAR_GP_PIN(3, 4), /* CANFD1_RX */
4120 [ 5] = RCAR_GP_PIN(3, 5), /* CANFD2_TX */
4121 [ 6] = RCAR_GP_PIN(3, 6), /* CANFD2_RX */
4122 [ 7] = RCAR_GP_PIN(3, 7), /* CANFD3_TX */
4123 [ 8] = RCAR_GP_PIN(3, 8), /* CANFD3_RX */
4124 [ 9] = RCAR_GP_PIN(3, 9), /* CANFD4_TX */
4125 [10] = RCAR_GP_PIN(3, 10), /* CANFD4_RX */
4126 [11] = RCAR_GP_PIN(3, 11), /* CANFD5_TX */
4127 [12] = RCAR_GP_PIN(3, 12), /* CANFD5_RX */
4128 [13] = RCAR_GP_PIN(3, 13), /* CANFD6_TX */
4129 [14] = RCAR_GP_PIN(3, 14), /* CANFD6_RX */
4130 [15] = RCAR_GP_PIN(3, 15), /* CANFD7_TX */
4131 [16] = RCAR_GP_PIN(3, 16), /* CANFD7_RX */
4149 [ 0] = RCAR_GP_PIN(4, 0), /* AVB0_RX_CTL */
4150 [ 1] = RCAR_GP_PIN(4, 1), /* AVB0_RXC */
4151 [ 2] = RCAR_GP_PIN(4, 2), /* AVB0_RD0 */
4152 [ 3] = RCAR_GP_PIN(4, 3), /* AVB0_RD1 */
4153 [ 4] = RCAR_GP_PIN(4, 4), /* AVB0_RD2 */
4154 [ 5] = RCAR_GP_PIN(4, 5), /* AVB0_RD3 */
4155 [ 6] = RCAR_GP_PIN(4, 6), /* AVB0_TX_CTL */
4156 [ 7] = RCAR_GP_PIN(4, 7), /* AVB0_TXC */
4157 [ 8] = RCAR_GP_PIN(4, 8), /* AVB0_TD0 */
4158 [ 9] = RCAR_GP_PIN(4, 9), /* AVB0_TD1 */
4159 [10] = RCAR_GP_PIN(4, 10), /* AVB0_TD2 */
4160 [11] = RCAR_GP_PIN(4, 11), /* AVB0_TD3 */
4161 [12] = RCAR_GP_PIN(4, 12), /* AVB0_TXREFCLK */
4162 [13] = RCAR_GP_PIN(4, 13), /* AVB0_MDIO */
4163 [14] = RCAR_GP_PIN(4, 14), /* AVB0_MDC */
4164 [15] = RCAR_GP_PIN(4, 15), /* AVB0_MAGIC */
4165 [16] = RCAR_GP_PIN(4, 16), /* AVB0_PHY_INT */
4166 [17] = RCAR_GP_PIN(4, 17), /* AVB0_LINK */
4167 [18] = RCAR_GP_PIN(4, 18), /* AVB0_AVTP_MATCH */
4168 [19] = RCAR_GP_PIN(4, 19), /* AVB0_AVTP_CAPTURE */
4169 [20] = RCAR_GP_PIN(4, 20), /* AVB0_AVTP_PPS */
4170 [21] = RCAR_GP_PIN(4, 21), /* PCIE0_CLKREQ_N */
4171 [22] = RCAR_GP_PIN(4, 22), /* PCIE1_CLKREQ_N */
4172 [23] = RCAR_GP_PIN(4, 23), /* PCIE2_CLKREQ_N */
4173 [24] = RCAR_GP_PIN(4, 24), /* PCIE3_CLKREQ_N */
4174 [25] = RCAR_GP_PIN(4, 25), /* AVS0 */
4175 [26] = RCAR_GP_PIN(4, 26), /* AVS1 */
4183 [ 0] = RCAR_GP_PIN(5, 0), /* AVB1_RX_CTL */
4184 [ 1] = RCAR_GP_PIN(5, 1), /* AVB1_RXC */
4185 [ 2] = RCAR_GP_PIN(5, 2), /* AVB1_RD0 */
4186 [ 3] = RCAR_GP_PIN(5, 3), /* AVB1_RD1 */
4187 [ 4] = RCAR_GP_PIN(5, 4), /* AVB1_RD2 */
4188 [ 5] = RCAR_GP_PIN(5, 5), /* AVB1_RD3 */
4189 [ 6] = RCAR_GP_PIN(5, 6), /* AVB1_TX_CTL */
4190 [ 7] = RCAR_GP_PIN(5, 7), /* AVB1_TXC */
4191 [ 8] = RCAR_GP_PIN(5, 8), /* AVB1_TD0 */
4192 [ 9] = RCAR_GP_PIN(5, 9), /* AVB1_TD1 */
4193 [10] = RCAR_GP_PIN(5, 10), /* AVB1_TD2 */
4194 [11] = RCAR_GP_PIN(5, 11), /* AVB1_TD3 */
4195 [12] = RCAR_GP_PIN(5, 12), /* AVB1_TXCREFCLK */
4196 [13] = RCAR_GP_PIN(5, 13), /* AVB1_MDIO */
4197 [14] = RCAR_GP_PIN(5, 14), /* AVB1_MDC */
4198 [15] = RCAR_GP_PIN(5, 15), /* AVB1_MAGIC */
4199 [16] = RCAR_GP_PIN(5, 16), /* AVB1_PHY_INT */
4200 [17] = RCAR_GP_PIN(5, 17), /* AVB1_LINK */
4201 [18] = RCAR_GP_PIN(5, 18), /* AVB1_AVTP_MATCH */
4202 [19] = RCAR_GP_PIN(5, 19), /* AVB1_AVTP_CAPTURE */
4203 [20] = RCAR_GP_PIN(5, 20), /* AVB1_AVTP_PPS */
4217 [ 0] = RCAR_GP_PIN(6, 0), /* AVB2_RX_CTL */
4218 [ 1] = RCAR_GP_PIN(6, 1), /* AVB2_RXC */
4219 [ 2] = RCAR_GP_PIN(6, 2), /* AVB2_RD0 */
4220 [ 3] = RCAR_GP_PIN(6, 3), /* AVB2_RD1 */
4221 [ 4] = RCAR_GP_PIN(6, 4), /* AVB2_RD2 */
4222 [ 5] = RCAR_GP_PIN(6, 5), /* AVB2_RD3 */
4223 [ 6] = RCAR_GP_PIN(6, 6), /* AVB2_TX_CTL */
4224 [ 7] = RCAR_GP_PIN(6, 7), /* AVB2_TXC */
4225 [ 8] = RCAR_GP_PIN(6, 8), /* AVB2_TD0 */
4226 [ 9] = RCAR_GP_PIN(6, 9), /* AVB2_TD1 */
4227 [10] = RCAR_GP_PIN(6, 10), /* AVB2_TD2 */
4228 [11] = RCAR_GP_PIN(6, 11), /* AVB2_TD3 */
4229 [12] = RCAR_GP_PIN(6, 12), /* AVB2_TXCREFCLK */
4230 [13] = RCAR_GP_PIN(6, 13), /* AVB2_MDIO */
4231 [14] = RCAR_GP_PIN(6, 14), /* AVB2_MDC */
4232 [15] = RCAR_GP_PIN(6, 15), /* AVB2_MAGIC */
4233 [16] = RCAR_GP_PIN(6, 16), /* AVB2_PHY_INT */
4234 [17] = RCAR_GP_PIN(6, 17), /* AVB2_LINK */
4235 [18] = RCAR_GP_PIN(6, 18), /* AVB2_AVTP_MATCH */
4236 [19] = RCAR_GP_PIN(6, 19), /* AVB2_AVTP_CAPTURE */
4237 [20] = RCAR_GP_PIN(6, 20), /* AVB2_AVTP_PPS */
4251 [ 0] = RCAR_GP_PIN(7, 0), /* AVB3_RX_CTL */
4252 [ 1] = RCAR_GP_PIN(7, 1), /* AVB3_RXC */
4253 [ 2] = RCAR_GP_PIN(7, 2), /* AVB3_RD0 */
4254 [ 3] = RCAR_GP_PIN(7, 3), /* AVB3_RD1 */
4255 [ 4] = RCAR_GP_PIN(7, 4), /* AVB3_RD2 */
4256 [ 5] = RCAR_GP_PIN(7, 5), /* AVB3_RD3 */
4257 [ 6] = RCAR_GP_PIN(7, 6), /* AVB3_TX_CTL */
4258 [ 7] = RCAR_GP_PIN(7, 7), /* AVB3_TXC */
4259 [ 8] = RCAR_GP_PIN(7, 8), /* AVB3_TD0 */
4260 [ 9] = RCAR_GP_PIN(7, 9), /* AVB3_TD1 */
4261 [10] = RCAR_GP_PIN(7, 10), /* AVB3_TD2 */
4262 [11] = RCAR_GP_PIN(7, 11), /* AVB3_TD3 */
4263 [12] = RCAR_GP_PIN(7, 12), /* AVB3_TXCREFCLK */
4264 [13] = RCAR_GP_PIN(7, 13), /* AVB3_MDIO */
4265 [14] = RCAR_GP_PIN(7, 14), /* AVB3_MDC */
4266 [15] = RCAR_GP_PIN(7, 15), /* AVB3_MAGIC */
4267 [16] = RCAR_GP_PIN(7, 16), /* AVB3_PHY_INT */
4268 [17] = RCAR_GP_PIN(7, 17), /* AVB3_LINK */
4269 [18] = RCAR_GP_PIN(7, 18), /* AVB3_AVTP_MATCH */
4270 [19] = RCAR_GP_PIN(7, 19), /* AVB3_AVTP_CAPTURE */
4271 [20] = RCAR_GP_PIN(7, 20), /* AVB3_AVTP_PPS */
4285 [ 0] = RCAR_GP_PIN(8, 0), /* AVB4_RX_CTL */
4286 [ 1] = RCAR_GP_PIN(8, 1), /* AVB4_RXC */
4287 [ 2] = RCAR_GP_PIN(8, 2), /* AVB4_RD0 */
4288 [ 3] = RCAR_GP_PIN(8, 3), /* AVB4_RD1 */
4289 [ 4] = RCAR_GP_PIN(8, 4), /* AVB4_RD2 */
4290 [ 5] = RCAR_GP_PIN(8, 5), /* AVB4_RD3 */
4291 [ 6] = RCAR_GP_PIN(8, 6), /* AVB4_TX_CTL */
4292 [ 7] = RCAR_GP_PIN(8, 7), /* AVB4_TXC */
4293 [ 8] = RCAR_GP_PIN(8, 8), /* AVB4_TD0 */
4294 [ 9] = RCAR_GP_PIN(8, 9), /* AVB4_TD1 */
4295 [10] = RCAR_GP_PIN(8, 10), /* AVB4_TD2 */
4296 [11] = RCAR_GP_PIN(8, 11), /* AVB4_TD3 */
4297 [12] = RCAR_GP_PIN(8, 12), /* AVB4_TXCREFCLK */
4298 [13] = RCAR_GP_PIN(8, 13), /* AVB4_MDIO */
4299 [14] = RCAR_GP_PIN(8, 14), /* AVB4_MDC */
4300 [15] = RCAR_GP_PIN(8, 15), /* AVB4_MAGIC */
4301 [16] = RCAR_GP_PIN(8, 16), /* AVB4_PHY_INT */
4302 [17] = RCAR_GP_PIN(8, 17), /* AVB4_LINK */
4303 [18] = RCAR_GP_PIN(8, 18), /* AVB4_AVTP_MATCH */
4304 [19] = RCAR_GP_PIN(8, 19), /* AVB4_AVTP_CAPTURE */
4305 [20] = RCAR_GP_PIN(8, 20), /* AVB4_AVTP_PPS */
4319 [ 0] = RCAR_GP_PIN(9, 0), /* AVB5_RX_CTL */
4320 [ 1] = RCAR_GP_PIN(9, 1), /* AVB5_RXC */
4321 [ 2] = RCAR_GP_PIN(9, 2), /* AVB5_RD0 */
4322 [ 3] = RCAR_GP_PIN(9, 3), /* AVB5_RD1 */
4323 [ 4] = RCAR_GP_PIN(9, 4), /* AVB5_RD2 */
4324 [ 5] = RCAR_GP_PIN(9, 5), /* AVB5_RD3 */
4325 [ 6] = RCAR_GP_PIN(9, 6), /* AVB5_TX_CTL */
4326 [ 7] = RCAR_GP_PIN(9, 7), /* AVB5_TXC */
4327 [ 8] = RCAR_GP_PIN(9, 8), /* AVB5_TD0 */
4328 [ 9] = RCAR_GP_PIN(9, 9), /* AVB5_TD1 */
4329 [10] = RCAR_GP_PIN(9, 10), /* AVB5_TD2 */
4330 [11] = RCAR_GP_PIN(9, 11), /* AVB5_TD3 */
4331 [12] = RCAR_GP_PIN(9, 12), /* AVB5_TXCREFCLK */
4332 [13] = RCAR_GP_PIN(9, 13), /* AVB5_MDIO */
4333 [14] = RCAR_GP_PIN(9, 14), /* AVB5_MDC */
4334 [15] = RCAR_GP_PIN(9, 15), /* AVB5_MAGIC */
4335 [16] = RCAR_GP_PIN(9, 16), /* AVB5_PHY_INT */
4336 [17] = RCAR_GP_PIN(9, 17), /* AVB5_LINK */
4337 [18] = RCAR_GP_PIN(9, 18), /* AVB5_AVTP_MATCH */
4338 [19] = RCAR_GP_PIN(9, 19), /* AVB5_AVTP_CAPTURE */
4339 [20] = RCAR_GP_PIN(9, 20), /* AVB5_AVTP_PPS */