pinctrl/qcom/pinctrl-ssbi-gpio.c

91 	struct pinctrl_dev *pctrl;
127 static int pm8xxx_read_bank(struct pm8xxx_gpio *pctrl,
133 	ret = regmap_write(pctrl->regmap, pin->reg, val);
135 		dev_err(pctrl->dev, "failed to select bank %d\n", bank);
139 	ret = regmap_read(pctrl->regmap, pin->reg, &val);
141 		dev_err(pctrl->dev, "failed to read register %d\n", bank);
148 static int pm8xxx_write_bank(struct pm8xxx_gpio *pctrl,
158 	ret = regmap_write(pctrl->regmap, pin->reg, val);
160 		dev_err(pctrl->dev, "failed to write register\n");
167 	struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
169 	return pctrl->npins;
184 	struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
186 	*pins = &pctrl->desc.pins[group].number;
216 	struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
219 	*num_groups = pctrl->npins;
227 	struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
228 	struct pm8xxx_pin_data *pin = pctrl->desc.pins[group].drv_data;
234 	pm8xxx_write_bank(pctrl, pin, 4, val);
250 	struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
251 	struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
320 	struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
321 	struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
347 				dev_err(pctrl->dev, "invalid pull-up strength\n");
377 				dev_err(pctrl->dev, "invalid drive strength\n");
392 			dev_err(pctrl->dev,
402 		pm8xxx_write_bank(pctrl, pin, 0, val);
409 		pm8xxx_write_bank(pctrl, pin, 1, val);
414 		pm8xxx_write_bank(pctrl, pin, 2, val);
420 		pm8xxx_write_bank(pctrl, pin, 3, val);
425 		pm8xxx_write_bank(pctrl, pin, 4, val);
432 		pm8xxx_write_bank(pctrl, pin, 5, val);
455 	struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
456 	struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
462 	pm8xxx_write_bank(pctrl, pin, 1, val);
471 	struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
472 	struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
482 	pm8xxx_write_bank(pctrl, pin, 1, val);
489 	struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
490 	struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
511 	struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
512 	struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
521 	pm8xxx_write_bank(pctrl, pin, 1, val);
546 	struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
547 	struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
604 static int pm8xxx_pin_populate(struct pm8xxx_gpio *pctrl,
609 	val = pm8xxx_read_bank(pctrl, pin, 0);
615 	val = pm8xxx_read_bank(pctrl, pin, 1);
623 	val = pm8xxx_read_bank(pctrl, pin, 2);
633 	val = pm8xxx_read_bank(pctrl, pin, 3);
640 	val = pm8xxx_read_bank(pctrl, pin, 4);
646 	val = pm8xxx_read_bank(pctrl, pin, 5);
686 	struct pm8xxx_gpio *pctrl = container_of(domain->host_data,
690 	    fwspec->param[0] > pctrl->chip.ngpio)
734 	struct pm8xxx_gpio *pctrl;
737 	pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
738 	if (!pctrl)
741 	pctrl->dev = &pdev->dev;
742 	pctrl->npins = (uintptr_t) device_get_match_data(&pdev->dev);
744 	pctrl->regmap = dev_get_regmap(pdev->dev.parent, NULL);
745 	if (!pctrl->regmap) {
750 	pctrl->desc = pm8xxx_pinctrl_desc;
751 	pctrl->desc.npins = pctrl->npins;
754 			    pctrl->desc.npins,
761 				pctrl->desc.npins,
767 	for (i = 0; i < pctrl->desc.npins; i++) {
770 		ret = pm8xxx_pin_populate(pctrl, &pin_data[i]);
778 	pctrl->desc.pins = pins;
780 	pctrl->desc.num_custom_params = ARRAY_SIZE(pm8xxx_gpio_bindings);
781 	pctrl->desc.custom_params = pm8xxx_gpio_bindings;
783 	pctrl->desc.custom_conf_items = pm8xxx_conf_items;
786 	pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl);
787 	if (IS_ERR(pctrl->pctrl)) {
789 		return PTR_ERR(pctrl->pctrl);
792 	pctrl->chip = pm8xxx_gpio_template;
793 	pctrl->chip.base = -1;
794 	pctrl->chip.parent = &pdev->dev;
795 	pctrl->chip.of_gpio_n_cells = 2;
796 	pctrl->chip.label = dev_name(pctrl->dev);
797 	pctrl->chip.ngpio = pctrl->npins;
799 	parent_node = of_irq_find_parent(pctrl->dev->of_node);
808 	girq = &pctrl->chip.irq;
812 	girq->fwnode = dev_fwnode(pctrl->dev);
819 	ret = gpiochip_add_data(&pctrl->chip, pctrl);
835 	if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) {
836 		ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
837 					     0, 0, pctrl->chip.ngpio);
839 			dev_err(pctrl->dev, "failed to add pin range\n");
844 	platform_set_drvdata(pdev, pctrl);
851 	gpiochip_remove(&pctrl->chip);
858 	struct pm8xxx_gpio *pctrl = platform_get_drvdata(pdev);
860 	gpiochip_remove(&pctrl->chip);