Lines Matching refs:pctl

26 	struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
28 return pctl->ngroups;
34 struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
35 struct pxa_pinctrl_group *group = pctl->groups + tgroup;
45 struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
46 struct pxa_pinctrl_group *group = pctl->groups + tgroup;
65 pxa_desc_by_func_group(struct pxa_pinctrl *pctl, const char *pin_name,
71 for (i = 0; i < pctl->npins; i++) {
72 const struct pxa_desc_pin *pin = pctl->ppins + i;
88 struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
93 gpdr = pctl->base_gpdr[pin / 32];
94 dev_dbg(pctl->dev, "set_direction(pin=%d): dir=%d\n",
97 spin_lock_irqsave(&pctl->lock, flags);
103 spin_unlock_irqrestore(&pctl->lock, flags);
111 struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
112 struct pxa_pinctrl_function *pf = pctl->functions + function;
119 struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
121 return pctl->nfuncs;
129 struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
130 struct pxa_pinctrl_function *pf = pctl->functions + function;
141 struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
142 struct pxa_pinctrl_group *group = pctl->groups + tgroup;
150 df = pxa_desc_by_func_group(pctl, group->name,
151 (pctl->functions + function)->name);
156 gafr = pctl->base_gafr[pin / 16];
157 gpdr = pctl->base_gpdr[pin / 32];
159 dev_dbg(pctl->dev, "set_mux(pin=%d): af=%d dir=%d\n",
162 spin_lock_irqsave(&pctl->lock, flags);
172 spin_unlock_irqrestore(&pctl->lock, flags);
188 struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
189 struct pxa_pinctrl_group *g = pctl->groups + group;
192 void __iomem *pgsr = pctl->base_pgsr[pin / 32];
195 spin_lock_irqsave(&pctl->lock, flags);
198 spin_unlock_irqrestore(&pctl->lock, flags);
200 dev_dbg(pctl->dev, "get sleep gpio state(pin=%d) %d\n",
210 struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
211 struct pxa_pinctrl_group *g = pctl->groups + group;
214 void __iomem *pgsr = pctl->base_pgsr[pin / 32];
228 dev_dbg(pctl->dev, "set sleep gpio state(pin=%d) %d\n",
231 spin_lock_irqsave(&pctl->lock, flags);
235 spin_unlock_irqrestore(&pctl->lock, flags);
253 pxa2xx_find_function(struct pxa_pinctrl *pctl, const char *fname,
265 static int pxa2xx_build_functions(struct pxa_pinctrl *pctl)
277 functions = devm_kcalloc(pctl->dev, pctl->npins * 6,
282 for (i = 0; i < pctl->npins; i++)
283 for (df = pctl->ppins[i].functions; df->name; df++)
284 if (!pxa2xx_find_function(pctl, df->name, functions))
285 (functions + pctl->nfuncs++)->name = df->name;
286 pctl->functions = devm_kmemdup(pctl->dev, functions,
287 pctl->nfuncs * sizeof(*functions),
289 if (!pctl->functions)
292 devm_kfree(pctl->dev, functions);
296 static int pxa2xx_build_groups(struct pxa_pinctrl *pctl)
303 gtmp = devm_kmalloc_array(pctl->dev, pctl->npins, sizeof(*gtmp),
308 for (i = 0; i < pctl->nfuncs; i++) {
310 for (j = 0; j < pctl->npins; j++)
311 for (df = pctl->ppins[j].functions; df->name;
313 if (!strcmp(pctl->functions[i].name,
316 pctl->ppins[j].pin.name;
317 func = pctl->functions + i;
320 devm_kmalloc_array(pctl->dev, ngroups,
328 devm_kfree(pctl->dev, gtmp);
332 static int pxa2xx_build_state(struct pxa_pinctrl *pctl,
339 pctl->npins = npins;
340 pctl->ppins = ppins;
341 pctl->ngroups = npins;
343 pctl->desc.npins = npins;
344 pins = devm_kcalloc(pctl->dev, npins, sizeof(*pins), GFP_KERNEL);
348 pctl->desc.pins = pins;
352 pctl->groups = devm_kmalloc_array(pctl->dev, pctl->ngroups,
353 sizeof(*pctl->groups), GFP_KERNEL);
354 if (!pctl->groups)
358 group = pctl->groups + i;
363 ret = pxa2xx_build_functions(pctl);
367 ret = pxa2xx_build_groups(pctl);
379 struct pxa_pinctrl *pctl;
385 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
386 if (!pctl)
388 pctl->base_gafr = devm_kcalloc(&pdev->dev, roundup(maxpin, 16),
389 sizeof(*pctl->base_gafr), GFP_KERNEL);
390 pctl->base_gpdr = devm_kcalloc(&pdev->dev, roundup(maxpin, 32),
391 sizeof(*pctl->base_gpdr), GFP_KERNEL);
392 pctl->base_pgsr = devm_kcalloc(&pdev->dev, roundup(maxpin, 32),
393 sizeof(*pctl->base_pgsr), GFP_KERNEL);
394 if (!pctl->base_gafr || !pctl->base_gpdr || !pctl->base_pgsr)
397 platform_set_drvdata(pdev, pctl);
398 spin_lock_init(&pctl->lock);
400 pctl->dev = &pdev->dev;
401 pctl->desc = pxa2xx_pinctrl_desc;
402 pctl->desc.name = dev_name(&pdev->dev);
403 pctl->desc.owner = THIS_MODULE;
406 pctl->base_gafr[i / 16] = base_gafr[i / 16];
408 pctl->base_gpdr[i / 32] = base_gpdr[i / 32];
409 pctl->base_pgsr[i / 32] = base_pgsr[i / 32];
412 ret = pxa2xx_build_state(pctl, ppins, npins);
416 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->desc, pctl);
417 if (IS_ERR(pctl->pctl_dev)) {
419 return PTR_ERR(pctl->pctl_dev);