Lines Matching refs:pcs
209 #define PCS_QUIRK_HAS_SHARED_IRQ (pcs->flags & PCS_QUIRK_SHARED_IRQ)
210 #define PCS_HAS_IRQ (pcs->flags & PCS_FEAT_IRQ)
211 #define PCS_HAS_PINCONF (pcs->flags & PCS_FEAT_PINCONF)
272 static unsigned int pcs_pin_reg_offset_get(struct pcs_device *pcs,
275 unsigned int mux_bytes = pcs->width / BITS_PER_BYTE;
277 if (pcs->bits_per_mux) {
280 pin_offset_bytes = (pcs->bits_per_pin * pin) / BITS_PER_BYTE;
287 static unsigned int pcs_pin_shift_reg_get(struct pcs_device *pcs,
290 return (pin % (pcs->width / pcs->bits_per_pin)) * pcs->bits_per_pin;
297 struct pcs_device *pcs;
302 pcs = pinctrl_dev_get_drvdata(pctldev);
304 offset = pcs_pin_reg_offset_get(pcs, pin);
305 val = pcs->read(pcs->base + offset);
307 if (pcs->bits_per_mux)
308 val &= pcs->fmask << pcs_pin_shift_reg_get(pcs, pin);
310 pa = pcs->res->start + offset;
318 struct pcs_device *pcs;
320 pcs = pinctrl_dev_get_drvdata(pctldev);
321 devm_kfree(pcs->dev, map);
340 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
354 dev_err(pcs->dev, "%s could not find function%i\n",
364 struct pcs_device *pcs;
369 pcs = pinctrl_dev_get_drvdata(pctldev);
371 if (!pcs->fmask)
380 dev_dbg(pcs->dev, "enabling %s function%i\n",
389 raw_spin_lock_irqsave(&pcs->lock, flags);
390 val = pcs->read(vals->reg);
392 if (pcs->bits_per_mux)
395 mask = pcs->fmask;
399 pcs->write(val, vals->reg);
400 raw_spin_unlock_irqrestore(&pcs->lock, flags);
409 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
415 if (!pcs->fmask)
418 list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {
426 offset = pcs_pin_reg_offset_get(pcs, pin);
428 if (pcs->bits_per_mux) {
429 int pin_shift = pcs_pin_shift_reg_get(pcs, pin);
431 data = pcs->read(pcs->base + offset);
432 data &= ~(pcs->fmask << pin_shift);
434 pcs->write(data, pcs->base + offset);
436 data = pcs->read(pcs->base + offset);
437 data &= ~pcs->fmask;
439 pcs->write(data, pcs->base + offset);
487 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
509 offset = pin * (pcs->width / BITS_PER_BYTE);
510 data = pcs->read(pcs->base + offset) & func->conf[i].mask;
552 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
568 offset = pin * (pcs->width / BITS_PER_BYTE);
569 data = pcs->read(pcs->base + offset);
601 pcs->write(data, pcs->base + offset);
681 * @pcs: pcs driver instance
684 static int pcs_add_pin(struct pcs_device *pcs, unsigned int offset)
686 struct pcs_soc_data *pcs_soc = &pcs->socdata;
690 i = pcs->pins.cur;
691 if (i >= pcs->desc.npins) {
692 dev_err(pcs->dev, "too many pins, max %i\n",
693 pcs->desc.npins);
700 val = pcs->read(pcs->base + offset);
702 dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n",
703 (unsigned long)pcs->res->start + offset, val);
705 pcs->write(val, pcs->base + offset);
709 pin = &pcs->pins.pa[i];
711 pcs->pins.cur++;
718 * @pcs: pcs driver instance
725 static int pcs_allocate_pin_table(struct pcs_device *pcs)
729 mux_bytes = pcs->width / BITS_PER_BYTE;
731 if (pcs->bits_per_mux && pcs->fmask) {
732 pcs->bits_per_pin = fls(pcs->fmask);
733 nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin;
735 nr_pins = pcs->size / mux_bytes;
738 dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins);
739 pcs->pins.pa = devm_kcalloc(pcs->dev,
740 nr_pins, sizeof(*pcs->pins.pa),
742 if (!pcs->pins.pa)
745 pcs->desc.pins = pcs->pins.pa;
746 pcs->desc.npins = nr_pins;
748 for (i = 0; i < pcs->desc.npins; i++) {
752 offset = pcs_pin_reg_offset_get(pcs, i);
753 res = pcs_add_pin(pcs, offset);
755 dev_err(pcs->dev, "error adding pins: %i\n", res);
765 * @pcs: pcs driver instance
775 static int pcs_add_function(struct pcs_device *pcs,
786 function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL);
794 selector = pinmux_generic_add_function(pcs->pctl, name,
798 devm_kfree(pcs->dev, function);
809 * @pcs: pcs driver instance
814 static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
818 if (offset >= pcs->size) {
819 dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n",
820 offset, pcs->size);
824 if (pcs->bits_per_mux)
825 index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin;
827 index = offset / (pcs->width / BITS_PER_BYTE);
868 static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np,
887 static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np,
899 dev_err(pcs->dev, "mask field of the property can't be 0\n");
907 dev_dbg(pcs->dev, "failed to match enable or disable bits\n");
912 static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
951 func->conf = devm_kcalloc(pcs->dev,
959 settings = devm_kcalloc(pcs->dev, nconfs, sizeof(unsigned long),
966 pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param,
969 pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param,
980 * @pcs: pinctrl driver instance
997 static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
1010 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
1014 vals = devm_kcalloc(pcs->dev, rows, sizeof(*vals), GFP_KERNEL);
1018 pins = devm_kcalloc(pcs->dev, rows, sizeof(*pins), GFP_KERNEL);
1032 dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1038 vals[found].reg = pcs->base + offset;
1049 dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x\n",
1052 pin = pcs_get_pin_by_offset(pcs, offset);
1054 dev_err(pcs->dev,
1063 mutex_lock(&pcs->mutex);
1064 fsel = pcs_add_function(pcs, &function, np->name, vals, found,
1071 gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1082 res = pcs_parse_pinconf(pcs, np, function, map);
1092 mutex_unlock(&pcs->mutex);
1097 pinctrl_generic_remove_group(pcs->pctl, gsel);
1100 pinmux_generic_remove_function(pcs->pctl, fsel);
1102 mutex_unlock(&pcs->mutex);
1103 devm_kfree(pcs->dev, pins);
1106 devm_kfree(pcs->dev, vals);
1111 static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
1125 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
1130 dev_err(pcs->dev, "pinconf not supported\n");
1134 npins_in_row = pcs->width / pcs->bits_per_pin;
1136 vals = devm_kzalloc(pcs->dev,
1142 pins = devm_kzalloc(pcs->dev,
1160 dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1170 dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x mask: 0x%x\n",
1176 pin_num_from_lsb = bit_pos / pcs->bits_per_pin;
1177 mask_pos = ((pcs->fmask) << bit_pos);
1182 dev_err(pcs->dev,
1191 dev_warn(pcs->dev,
1198 vals[found].reg = pcs->base + offset;
1201 pin = pcs_get_pin_by_offset(pcs, offset);
1203 dev_err(pcs->dev,
1213 mutex_lock(&pcs->mutex);
1214 fsel = pcs_add_function(pcs, &function, np->name, vals, found,
1221 res = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1230 mutex_unlock(&pcs->mutex);
1235 pinmux_generic_remove_function(pcs->pctl, fsel);
1237 mutex_unlock(&pcs->mutex);
1238 devm_kfree(pcs->dev, pins);
1241 devm_kfree(pcs->dev, vals);
1256 struct pcs_device *pcs;
1260 pcs = pinctrl_dev_get_drvdata(pctldev);
1263 *map = devm_kcalloc(pcs->dev, 2, sizeof(**map), GFP_KERNEL);
1269 pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL);
1275 if (pcs->bits_per_mux) {
1276 ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map,
1279 dev_err(pcs->dev, "no pins entries for %pOFn\n",
1284 ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map,
1287 dev_err(pcs->dev, "no pins entries for %pOFn\n",
1296 devm_kfree(pcs->dev, pgnames);
1298 devm_kfree(pcs->dev, *map);
1305 * @pcs: pcs driver instance
1307 static void pcs_irq_free(struct pcs_device *pcs)
1309 struct pcs_soc_data *pcs_soc = &pcs->socdata;
1314 if (pcs->domain)
1315 irq_domain_remove(pcs->domain);
1325 * @pcs: pcs driver instance
1327 static void pcs_free_resources(struct pcs_device *pcs)
1329 pcs_irq_free(pcs);
1330 pinctrl_unregister(pcs->pctl);
1333 if (pcs->missing_nr_pinctrl_cells)
1334 of_remove_property(pcs->np, pcs->missing_nr_pinctrl_cells);
1338 static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
1354 range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL);
1362 mutex_lock(&pcs->mutex);
1363 list_add_tail(&range->node, &pcs->gpiofuncs);
1364 mutex_unlock(&pcs->mutex);
1395 struct pcs_device *pcs;
1399 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1400 list_for_each(pos, &pcs->irqs) {
1409 raw_spin_lock(&pcs->lock);
1410 mask = pcs->read(pcswi->reg);
1415 pcs->write(mask, pcswi->reg);
1418 mask = pcs->read(pcswi->reg);
1419 raw_spin_unlock(&pcs->lock);
1476 struct pcs_device *pcs;
1480 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1481 list_for_each(pos, &pcs->irqs) {
1486 raw_spin_lock(&pcs->lock);
1487 mask = pcs->read(pcswi->reg);
1488 raw_spin_unlock(&pcs->lock);
1490 generic_handle_domain_irq(pcs->domain,
1537 struct pcs_device *pcs;
1540 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1541 pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL);
1545 pcswi->reg = pcs->base + hwirq;
1549 mutex_lock(&pcs->mutex);
1550 list_add_tail(&pcswi->node, &pcs->irqs);
1551 mutex_unlock(&pcs->mutex);
1554 irq_set_chip_and_handler(irq, &pcs->chip,
1569 * @pcs: pcs driver instance
1572 static int pcs_irq_init_chained_handler(struct pcs_device *pcs,
1575 struct pcs_soc_data *pcs_soc = &pcs->socdata;
1585 INIT_LIST_HEAD(&pcs->irqs);
1586 pcs->chip.name = name;
1587 pcs->chip.irq_ack = pcs_irq_mask;
1588 pcs->chip.irq_mask = pcs_irq_mask;
1589 pcs->chip.irq_unmask = pcs_irq_unmask;
1590 pcs->chip.irq_set_wake = pcs_irq_set_wake;
1615 num_irqs = pcs->size;
1617 pcs->domain = irq_domain_add_simple(np, num_irqs, 0,
1620 if (!pcs->domain) {
1629 static int pcs_save_context(struct pcs_device *pcs)
1636 mux_bytes = pcs->width / BITS_PER_BYTE;
1638 if (!pcs->saved_vals) {
1639 pcs->saved_vals = devm_kzalloc(pcs->dev, pcs->size, GFP_ATOMIC);
1640 if (!pcs->saved_vals)
1644 switch (pcs->width) {
1646 regsl = pcs->saved_vals;
1647 for (i = 0; i < pcs->size; i += mux_bytes)
1648 *regsl++ = pcs->read(pcs->base + i);
1651 regsw = pcs->saved_vals;
1652 for (i = 0; i < pcs->size; i += mux_bytes)
1653 *regsw++ = pcs->read(pcs->base + i);
1656 regshw = pcs->saved_vals;
1657 for (i = 0; i < pcs->size; i += mux_bytes)
1658 *regshw++ = pcs->read(pcs->base + i);
1665 static void pcs_restore_context(struct pcs_device *pcs)
1672 mux_bytes = pcs->width / BITS_PER_BYTE;
1674 switch (pcs->width) {
1676 regsl = pcs->saved_vals;
1677 for (i = 0; i < pcs->size; i += mux_bytes)
1678 pcs->write(*regsl++, pcs->base + i);
1681 regsw = pcs->saved_vals;
1682 for (i = 0; i < pcs->size; i += mux_bytes)
1683 pcs->write(*regsw++, pcs->base + i);
1686 regshw = pcs->saved_vals;
1687 for (i = 0; i < pcs->size; i += mux_bytes)
1688 pcs->write(*regshw++, pcs->base + i);
1696 struct pcs_device *pcs;
1698 pcs = platform_get_drvdata(pdev);
1699 if (!pcs)
1702 if (pcs->flags & PCS_CONTEXT_LOSS_OFF) {
1705 ret = pcs_save_context(pcs);
1710 return pinctrl_force_sleep(pcs->pctl);
1715 struct pcs_device *pcs;
1717 pcs = platform_get_drvdata(pdev);
1718 if (!pcs)
1721 if (pcs->flags & PCS_CONTEXT_LOSS_OFF)
1722 pcs_restore_context(pcs);
1724 return pinctrl_force_default(pcs->pctl);
1730 * @pcs: pinctrl driver instance
1738 static int pcs_quirk_missing_pinctrl_cells(struct pcs_device *pcs,
1751 dev_warn(pcs->dev, "please update dts to use %s = <%i>\n",
1754 p = devm_kzalloc(pcs->dev, sizeof(*p), GFP_KERNEL);
1759 p->value = devm_kzalloc(pcs->dev, sizeof(__be32), GFP_KERNEL);
1764 p->name = devm_kstrdup(pcs->dev, name, GFP_KERNEL);
1768 pcs->missing_nr_pinctrl_cells = p;
1771 error = of_add_property(np, pcs->missing_nr_pinctrl_cells);
1782 struct pcs_device *pcs;
1790 pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL);
1791 if (!pcs)
1794 pcs->dev = &pdev->dev;
1795 pcs->np = np;
1796 raw_spin_lock_init(&pcs->lock);
1797 mutex_init(&pcs->mutex);
1798 INIT_LIST_HEAD(&pcs->gpiofuncs);
1799 pcs->flags = soc->flags;
1800 memcpy(&pcs->socdata, soc, sizeof(*soc));
1803 &pcs->width);
1805 dev_err(pcs->dev, "register width not specified\n");
1811 &pcs->fmask);
1813 pcs->fshift = __ffs(pcs->fmask);
1814 pcs->fmax = pcs->fmask >> pcs->fshift;
1817 pcs->fmask = 0;
1818 pcs->fshift = 0;
1819 pcs->fmax = 0;
1823 &pcs->foff);
1825 pcs->foff = PCS_OFF_DISABLED;
1827 pcs->bits_per_mux = of_property_read_bool(np,
1829 ret = pcs_quirk_missing_pinctrl_cells(pcs, np,
1830 pcs->bits_per_mux ? 2 : 1);
1839 dev_err(pcs->dev, "could not get resource\n");
1843 pcs->res = devm_request_mem_region(pcs->dev, res->start,
1845 if (!pcs->res) {
1846 dev_err(pcs->dev, "could not get mem_region\n");
1850 pcs->size = resource_size(pcs->res);
1851 pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size);
1852 if (!pcs->base) {
1853 dev_err(pcs->dev, "could not ioremap\n");
1857 platform_set_drvdata(pdev, pcs);
1859 switch (pcs->width) {
1861 pcs->read = pcs_readb;
1862 pcs->write = pcs_writeb;
1865 pcs->read = pcs_readw;
1866 pcs->write = pcs_writew;
1869 pcs->read = pcs_readl;
1870 pcs->write = pcs_writel;
1876 pcs->desc.name = DRIVER_NAME;
1877 pcs->desc.pctlops = &pcs_pinctrl_ops;
1878 pcs->desc.pmxops = &pcs_pinmux_ops;
1880 pcs->desc.confops = &pcs_pinconf_ops;
1881 pcs->desc.owner = THIS_MODULE;
1883 ret = pcs_allocate_pin_table(pcs);
1887 ret = pinctrl_register_and_init(&pcs->desc, pcs->dev, pcs, &pcs->pctl);
1889 dev_err(pcs->dev, "could not register single pinctrl driver\n");
1893 ret = pcs_add_gpio_func(np, pcs);
1897 pcs->socdata.irq = irq_of_parse_and_map(np, 0);
1898 if (pcs->socdata.irq)
1899 pcs->flags |= PCS_FEAT_IRQ;
1905 pcs->socdata.rearm = pdata->rearm;
1907 pcs->socdata.irq = pdata->irq;
1908 pcs->flags |= PCS_FEAT_IRQ;
1913 ret = pcs_irq_init_chained_handler(pcs, np);
1915 dev_warn(pcs->dev, "initialized with no interrupts\n");
1918 dev_info(pcs->dev, "%i pins, size %u\n", pcs->desc.npins, pcs->size);
1920 return pinctrl_enable(pcs->pctl);
1923 pcs_free_resources(pcs);
1930 struct pcs_device *pcs = platform_get_drvdata(pdev);
1932 pcs_free_resources(pcs);