drivers/pinctrl/pinctrl-pistachio.c

95 	struct pistachio_pinctrl *pctl;
832 static inline u32 pctl_readl(struct pistachio_pinctrl *pctl, u32 reg)
834 	return readl(pctl->base + reg);
837 static inline void pctl_writel(struct pistachio_pinctrl *pctl, u32 val, u32 reg)
839 	writel(val, pctl->base + reg);
882 	struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
884 	return pctl->ngroups;
890 	struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
892 	return pctl->groups[group].name;
900 	struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
902 	*pins = &pctl->groups[group].pin;
918 	struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
920 	return pctl->nfunctions;
926 	struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
928 	return pctl->functions[func].name;
936 	struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
938 	*groups = pctl->functions[func].groups;
939 	*num_groups = pctl->functions[func].ngroups;
947 	struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
948 	const struct pistachio_pin_group *pg = &pctl->groups[group];
949 	const struct pistachio_function *pf = &pctl->functions[func];
960 			dev_err(pctl->dev, "Cannot mux pin %u to function %u\n",
965 		val = pctl_readl(pctl, pg->mux_reg);
968 		pctl_writel(pctl, val, pg->mux_reg);
978 			val = pctl_readl(pctl, pf->scenario_reg);
981 			pctl_writel(pctl, val, pf->scenario_reg);
985 	range = pinctrl_find_gpio_range_from_pin(pctl->pctldev, pg->pin);
1002 	struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1008 		val = pctl_readl(pctl, PADS_SCHMITT_EN_REG(pin));
1012 		val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
1017 		val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
1022 		val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
1027 		val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
1032 		val = pctl_readl(pctl, PADS_SLEW_RATE_REG(pin));
1036 		val = pctl_readl(pctl, PADS_DRIVE_STRENGTH_REG(pin)) >>
1055 		dev_dbg(pctl->dev, "Property %u not supported\n", param);
1067 	struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1078 			val = pctl_readl(pctl, PADS_SCHMITT_EN_REG(pin));
1083 			pctl_writel(pctl, val, PADS_SCHMITT_EN_REG(pin));
1086 			val = pctl_readl(pctl, PADS_PU_PD_REG(pin));
1089 			pctl_writel(pctl, val, PADS_PU_PD_REG(pin));
1092 			val = pctl_readl(pctl, PADS_PU_PD_REG(pin));
1095 			pctl_writel(pctl, val, PADS_PU_PD_REG(pin));
1098 			val = pctl_readl(pctl, PADS_PU_PD_REG(pin));
1101 			pctl_writel(pctl, val, PADS_PU_PD_REG(pin));
1104 			val = pctl_readl(pctl, PADS_PU_PD_REG(pin));
1107 			pctl_writel(pctl, val, PADS_PU_PD_REG(pin));
1110 			val = pctl_readl(pctl, PADS_SLEW_RATE_REG(pin));
1115 			pctl_writel(pctl, val, PADS_SLEW_RATE_REG(pin));
1118 			val = pctl_readl(pctl, PADS_DRIVE_STRENGTH_REG(pin));
1135 				dev_err(pctl->dev,
1141 			pctl_writel(pctl, val, PADS_DRIVE_STRENGTH_REG(pin));
1144 			dev_err(pctl->dev, "Property %u not supported\n",
1363 static int pistachio_gpio_register(struct pistachio_pinctrl *pctl)
1369 	for (i = 0; i < pctl->nbanks; i++) {
1375 		child = device_get_named_child_node(pctl->dev, child_name);
1377 			dev_err(pctl->dev, "No node for bank %u\n", i);
1384 			dev_err(pctl->dev,
1393 			dev_err(pctl->dev, "Failed to retrieve IRQ for bank %u\n", i);
1398 			dev_err(pctl->dev, "No IRQ for bank %u\n", i);
1404 		bank = &pctl->gpio_banks[i];
1405 		bank->pctl = pctl;
1406 		bank->base = pctl->base + GPIO_BANK_BASE(i);
1408 		bank->gpio_chip.parent = pctl->dev;
1415 		girq->parents = devm_kcalloc(pctl->dev, 1,
1428 			dev_err(pctl->dev, "Failed to add GPIO chip %u: %d\n",
1434 					     dev_name(pctl->dev), 0,
1437 			dev_err(pctl->dev, "Failed to add GPIO range %u: %d\n",
1447 		bank = &pctl->gpio_banks[i - 1];
1460 	struct pistachio_pinctrl *pctl;
1462 	pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1463 	if (!pctl)
1465 	pctl->dev = &pdev->dev;
1466 	dev_set_drvdata(&pdev->dev, pctl);
1468 	pctl->base = devm_platform_ioremap_resource(pdev, 0);
1469 	if (IS_ERR(pctl->base))
1470 		return PTR_ERR(pctl->base);
1472 	pctl->pins = pistachio_pins;
1473 	pctl->npins = ARRAY_SIZE(pistachio_pins);
1474 	pctl->functions = pistachio_functions;
1475 	pctl->nfunctions = ARRAY_SIZE(pistachio_functions);
1476 	pctl->groups = pistachio_groups;
1477 	pctl->ngroups = ARRAY_SIZE(pistachio_groups);
1478 	pctl->gpio_banks = pistachio_gpio_banks;
1479 	pctl->nbanks = ARRAY_SIZE(pistachio_gpio_banks);
1481 	pistachio_pinctrl_desc.pins = pctl->pins;
1482 	pistachio_pinctrl_desc.npins = pctl->npins;
1484 	pctl->pctldev = devm_pinctrl_register(&pdev->dev, &pistachio_pinctrl_desc,
1485 					      pctl);
1486 	if (IS_ERR(pctl->pctldev)) {
1488 		return PTR_ERR(pctl->pctldev);
1491 	return pistachio_gpio_register(pctl);