drivers/pinctrl/pinctrl-pic32.c

1699 static inline struct pic32_gpio_bank *pctl_to_bank(struct pic32_pinctrl *pctl,
1702 	return &pctl->gpio_banks[pin / PINS_PER_BANK];
1707 	struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1709 	return pctl->ngroups;
1715 	struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1717 	return pctl->groups[group].name;
1725 	struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1727 	*pins = &pctl->groups[group].pin;
1743 	struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1745 	return pctl->nfunctions;
1751 	struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1753 	return pctl->functions[func].name;
1761 	struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1763 	*groups = pctl->functions[func].groups;
1764 	*num_groups = pctl->functions[func].ngroups;
1772 	struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1773 	const struct pic32_pin_group *pg = &pctl->groups[group];
1774 	const struct pic32_function *pf = &pctl->functions[func];
1780 			dev_dbg(pctl->dev,
1784 			writel(functions->muxval, pctl->reg_base + functions->muxreg);
1792 	dev_err(pctl->dev, "cannot mux pin %u to function %u\n", group, func);
1801 	struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1805 	dev_dbg(pctl->dev, "requesting gpio %d in bank %d with mask 0x%x\n",
1881 	struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1882 	struct pic32_gpio_bank *bank = pctl_to_bank(pctl, pin);
1910 		dev_err(pctl->dev, "Property %u not supported\n", param);
1922 	struct pic32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1923 	struct pic32_gpio_bank *bank = pctl_to_bank(pctl, pin);
1930 	dev_dbg(pctl->dev, "setting pin %d bank %d mask 0x%x\n",
1939 			dev_dbg(pctl->dev, "   pullup\n");
1943 			dev_dbg(pctl->dev, "   pulldown\n");
1947 			dev_dbg(pctl->dev, "   digital\n");
1951 			dev_dbg(pctl->dev, "   analog\n");
1955 			dev_dbg(pctl->dev, "   opendrain\n");
1966 			dev_err(pctl->dev, "Property %u not supported\n",
2163 	struct pic32_pinctrl *pctl;
2166 	pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
2167 	if (!pctl)
2169 	pctl->dev = &pdev->dev;
2170 	dev_set_drvdata(&pdev->dev, pctl);
2172 	pctl->reg_base = devm_platform_ioremap_resource(pdev, 0);
2173 	if (IS_ERR(pctl->reg_base))
2174 		return PTR_ERR(pctl->reg_base);
2176 	pctl->clk = devm_clk_get(&pdev->dev, NULL);
2177 	if (IS_ERR(pctl->clk)) {
2178 		ret = PTR_ERR(pctl->clk);
2183 	ret = clk_prepare_enable(pctl->clk);
2189 	pctl->pins = pic32_pins;
2190 	pctl->npins = ARRAY_SIZE(pic32_pins);
2191 	pctl->functions = pic32_functions;
2192 	pctl->nfunctions = ARRAY_SIZE(pic32_functions);
2193 	pctl->groups = pic32_groups;
2194 	pctl->ngroups = ARRAY_SIZE(pic32_groups);
2195 	pctl->gpio_banks = pic32_gpio_banks;
2196 	pctl->nbanks = ARRAY_SIZE(pic32_gpio_banks);
2198 	pic32_pinctrl_desc.pins = pctl->pins;
2199 	pic32_pinctrl_desc.npins = pctl->npins;
2203 	pctl->pctldev = devm_pinctrl_register(&pdev->dev, &pic32_pinctrl_desc,
2204 					      pctl);
2205 	if (IS_ERR(pctl->pctldev)) {
2207 		return PTR_ERR(pctl->pctldev);