drivers/pinctrl/pinctrl-palmas.c

559 static int palmas_pinctrl_get_pin_mux(struct palmas_pctrl_chip_info *pci)
566 	for (i = 0; i < pci->num_pin_groups; ++i) {
567 		g = &pci->pin_groups[i];
569 			pci->pins_current_opt[i] = 0;
572 		ret = palmas_read(pci->palmas, g->mux_reg_base,
575 			dev_err(pci->dev, "mux_reg 0x%02x read failed: %d\n",
580 		pci->pins_current_opt[i] = val >> g->mux_bit_shift;
585 static int palmas_pinctrl_set_dvfs1(struct palmas_pctrl_chip_info *pci,
592 	ret = palmas_update_bits(pci->palmas, PALMAS_PU_PD_OD_BASE,
596 		dev_err(pci->dev, "SECONDARY_PAD3 update failed %d\n", ret);
600 static int palmas_pinctrl_set_dvfs2(struct palmas_pctrl_chip_info *pci,
607 	ret = palmas_update_bits(pci->palmas, PALMAS_PU_PD_OD_BASE,
611 		dev_err(pci->dev, "SECONDARY_PAD3 update failed %d\n", ret);
617 	struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
619 	return pci->num_pin_groups;
625 	struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
627 	return pci->pin_groups[group].name;
633 	struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
635 	*pins = pci->pin_groups[group].pins;
636 	*num_pins = pci->pin_groups[group].npins;
650 	struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
652 	return pci->num_functions;
658 	struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
660 	return pci->functions[function].name;
667 	struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
669 	*groups = pci->functions[function].groups;
670 	*num_groups = pci->functions[function].ngroups;
678 	struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
683 	g = &pci->pin_groups[group];
688 			dev_err(pci->dev, "Pin %s does not support option %d\n",
701 			dev_err(pci->dev, "Pin %s does not support option %d\n",
713 	dev_dbg(pci->dev, "%s(): Base0x%02x:0x%02x:0x%02x:0x%02x\n",
717 	ret = palmas_update_bits(pci->palmas, g->mux_reg_base, g->mux_reg_add,
720 		dev_err(pci->dev, "Reg 0x%02x update failed: %d\n",
724 	pci->pins_current_opt[group] = i;
738 	struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
749 	for (group_nr = 0; group_nr < pci->num_pin_groups; ++group_nr) {
750 		if (pci->pin_groups[group_nr].pins[0] == pin)
754 	if (group_nr == pci->num_pin_groups) {
755 		dev_err(pci->dev,
760 	g = &pci->pin_groups[group_nr];
761 	opt = g->opt[pci->pins_current_opt[group_nr]];
763 		dev_err(pci->dev,
773 			dev_err(pci->dev,
780 		ret = palmas_read(pci->palmas, base, add, &val);
782 			dev_err(pci->dev, "Reg 0x%02x read failed: %d\n",
805 			dev_err(pci->dev,
812 		ret = palmas_read(pci->palmas, base, add, &val);
814 			dev_err(pci->dev, "Reg 0x%02x read failed: %d\n",
827 			dev_err(pci->dev,
835 		dev_err(pci->dev, "Properties not supported\n");
847 	struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
858 	for (group_nr = 0; group_nr < pci->num_pin_groups; ++group_nr) {
859 		if (pci->pin_groups[group_nr].pins[0] == pin)
863 	if (group_nr == pci->num_pin_groups) {
864 		dev_err(pci->dev,
869 	g = &pci->pin_groups[group_nr];
870 	opt = g->opt[pci->pins_current_opt[group_nr]];
872 		dev_err(pci->dev,
886 				dev_err(pci->dev,
903 				dev_err(pci->dev,
912 				dev_err(pci->dev,
925 				dev_err(pci->dev,
932 			dev_err(pci->dev, "Properties not supported\n");
936 		dev_dbg(pci->dev, "%s(): Add0x%02x:0x%02x:0x%02x:0x%02x\n",
938 		ret = palmas_update_bits(pci->palmas, base, add, mask, rval);
940 			dev_err(pci->dev, "Reg 0x%02x update failed: %d\n",
986 	struct palmas_pctrl_chip_info *pci;
1000 	pci = devm_kzalloc(&pdev->dev, sizeof(*pci), GFP_KERNEL);
1001 	if (!pci)
1004 	pci->dev = &pdev->dev;
1005 	pci->palmas = dev_get_drvdata(pdev->dev.parent);
1007 	pci->pins = palmas_pins_desc;
1008 	pci->num_pins = ARRAY_SIZE(palmas_pins_desc);
1009 	pci->functions = palmas_pin_function;
1010 	pci->num_functions = ARRAY_SIZE(palmas_pin_function);
1011 	pci->pin_groups = pinctrl_data->pin_groups;
1012 	pci->num_pin_groups = pinctrl_data->num_pin_groups;
1014 	platform_set_drvdata(pdev, pci);
1016 	palmas_pinctrl_set_dvfs1(pci, enable_dvfs1);
1017 	palmas_pinctrl_set_dvfs2(pci, enable_dvfs2);
1018 	ret = palmas_pinctrl_get_pin_mux(pci);
1028 	pci->pctl = devm_pinctrl_register(&pdev->dev, &palmas_pinctrl_desc,
1029 					  pci);
1030 	if (IS_ERR(pci->pctl)) {
1032 		return PTR_ERR(pci->pctl);