drivers/pinctrl/pinctrl-keembay.c

888 static void keembay_gpio_invert(struct keembay_pinctrl *kpc, unsigned int pin)
890 	unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
899 	keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin);
902 static void keembay_gpio_restore_default(struct keembay_pinctrl *kpc, unsigned int pin)
904 	unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
907 	keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin);
913 	struct keembay_pinctrl *kpc = pinctrl_dev_get_drvdata(pctldev);
916 	if (pin >= kpc->npins)
919 	val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
932 	struct keembay_pinctrl *kpc = pinctrl_dev_get_drvdata(pctldev);
951 	val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
953 	keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin);
958 static u32 keembay_pinconf_get_pull(struct keembay_pinctrl *kpc, unsigned int pin)
960 	unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
965 static int keembay_pinconf_set_pull(struct keembay_pinctrl *kpc, unsigned int pin,
968 	unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
971 	keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin);
976 static int keembay_pinconf_get_drive(struct keembay_pinctrl *kpc, unsigned int pin)
978 	unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
987 static int keembay_pinconf_set_drive(struct keembay_pinctrl *kpc, unsigned int pin,
990 	unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
995 	keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin);
1000 static int keembay_pinconf_get_slew_rate(struct keembay_pinctrl *kpc, unsigned int pin)
1002 	unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
1007 static int keembay_pinconf_set_slew_rate(struct keembay_pinctrl *kpc, unsigned int pin,
1010 	unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
1017 	keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin);
1022 static int keembay_pinconf_get_schmitt(struct keembay_pinctrl *kpc, unsigned int pin)
1024 	unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
1029 static int keembay_pinconf_set_schmitt(struct keembay_pinctrl *kpc, unsigned int pin,
1032 	unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
1039 	keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin);
1047 	struct keembay_pinctrl *kpc = pinctrl_dev_get_drvdata(pctldev);
1051 	if (pin >= kpc->npins)
1056 		if (keembay_pinconf_get_pull(kpc, pin) != KEEMBAY_GPIO_DISABLE)
1061 		if (keembay_pinconf_get_pull(kpc, pin) != KEEMBAY_GPIO_PULL_UP)
1066 		if (keembay_pinconf_get_pull(kpc, pin) != KEEMBAY_GPIO_PULL_DOWN)
1071 		if (keembay_pinconf_get_pull(kpc, pin) != KEEMBAY_GPIO_BUS_HOLD)
1076 		if (!keembay_pinconf_get_schmitt(kpc, pin))
1081 		val = keembay_pinconf_get_slew_rate(kpc, pin);
1086 		val = keembay_pinconf_get_drive(kpc, pin);
1100 	struct keembay_pinctrl *kpc = pinctrl_dev_get_drvdata(pctldev);
1105 	if (pin >= kpc->npins)
1114 			ret = keembay_pinconf_set_pull(kpc, pin, KEEMBAY_GPIO_DISABLE);
1118 			ret = keembay_pinconf_set_pull(kpc, pin, KEEMBAY_GPIO_PULL_UP);
1122 			ret = keembay_pinconf_set_pull(kpc, pin, KEEMBAY_GPIO_PULL_DOWN);
1126 			ret = keembay_pinconf_set_pull(kpc, pin, KEEMBAY_GPIO_BUS_HOLD);
1130 			ret = keembay_pinconf_set_schmitt(kpc, pin, arg);
1134 			ret = keembay_pinconf_set_slew_rate(kpc, pin, arg);
1138 			ret = keembay_pinconf_set_drive(kpc, pin, arg);
1182 	struct keembay_pinctrl *kpc = gpiochip_get_data(gc);
1185 	val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
1188 	return keembay_read_pin(kpc->base0 + offset, pin);
1193 	struct keembay_pinctrl *kpc = gpiochip_get_data(gc);
1196 	reg_val = keembay_read_gpio_reg(kpc->base0 + KEEMBAY_GPIO_DATA_OUT, pin);
1199 				       kpc->base0 + KEEMBAY_GPIO_DATA_HIGH, pin);
1202 				       kpc->base0 + KEEMBAY_GPIO_DATA_LOW, pin);
1207 	struct keembay_pinctrl *kpc = gpiochip_get_data(gc);
1208 	unsigned int val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
1215 	struct keembay_pinctrl *kpc = gpiochip_get_data(gc);
1218 	val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
1220 	keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin);
1228 	struct keembay_pinctrl *kpc = gpiochip_get_data(gc);
1231 	val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_MODE, pin);
1233 	keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_MODE, pin);
1245 	struct keembay_pinctrl *kpc;
1258 	kpc = gpiochip_get_data(gc);
1261 	reg = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_INT_CFG, src);
1270 		val = keembay_read_pin(kpc->base0 + KEEMBAY_GPIO_DATA_IN, pin);
1284 	struct keembay_pinctrl *kpc = gpiochip_get_data(gc);
1286 	struct keembay_gpio_irq *irq = &kpc->irq[src];
1294 	val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_INT_CFG, src);
1297 	keembay_write_reg(val, kpc->base1 + KEEMBAY_GPIO_INT_CFG, src);
1303 		keembay_gpio_restore_default(kpc, pin);
1306 		kpc->max_gpios_level_type++;
1308 		kpc->max_gpios_edge_type++;
1311 static int keembay_find_free_slot(struct keembay_pinctrl *kpc, unsigned int src)
1313 	unsigned long val = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_INT_CFG, src);
1318 static int keembay_find_free_src(struct keembay_pinctrl *kpc, unsigned int trig)
1328 		if (kpc->irq[src].trigger != type)
1331 		if (!keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_INT_CFG, src) ||
1332 		    kpc->irq[src].num_share < KEEMBAY_GPIO_MAX_PER_IRQ)
1339 static void keembay_gpio_set_irq(struct keembay_pinctrl *kpc, int src,
1343 	struct keembay_gpio_irq *irq = &kpc->irq[src];
1346 	raw_spin_lock_irqsave(&kpc->lock, flags);
1347 	reg = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_INT_CFG, src);
1349 	keembay_write_reg(reg, kpc->base1 + KEEMBAY_GPIO_INT_CFG, src);
1350 	raw_spin_unlock_irqrestore(&kpc->lock, flags);
1353 		kpc->max_gpios_level_type--;
1355 		kpc->max_gpios_edge_type--;
1365 	struct keembay_pinctrl *kpc = gpiochip_get_data(gc);
1371 	src = keembay_find_free_src(kpc, trig);
1372 	slot = keembay_find_free_slot(kpc, src);
1378 		keembay_gpio_invert(kpc, pin);
1380 	keembay_gpio_set_irq(kpc, src, slot, pin);
1399 	struct keembay_pinctrl *kpc = gpiochip_get_data(gc);
1405 		reg = keembay_read_reg(kpc->base1 + KEEMBAY_GPIO_INT_CFG, src);
1418 	struct keembay_pinctrl *kpc = gpiochip_get_data(gc);
1421 	if (!kpc->max_gpios_edge_type && (type & IRQ_TYPE_EDGE_BOTH))
1424 	if (!kpc->max_gpios_level_type && (type & IRQ_TYPE_LEVEL_MASK))
1439 	struct keembay_pinctrl *kpc = gpiochip_get_data(chip);
1442 	ret = gpiochip_add_pin_range(chip, dev_name(kpc->dev), 0, 0, chip->ngpio);
1444 		dev_err_probe(kpc->dev, ret, "failed to add GPIO pin range\n");
1456 static int keembay_gpiochip_probe(struct keembay_pinctrl *kpc,
1460 	struct gpio_chip *gc = &kpc->chip;
1464 	girq			= &kpc->chip.irq;
1468 	girq->parents		= devm_kcalloc(kpc->dev, girq->num_parents,
1475 	gc->label		= dev_name(kpc->dev);
1476 	gc->parent		= kpc->dev;
1486 	gc->ngpio		= kpc->npins;
1490 		struct keembay_gpio_irq *kmb_irq = &kpc->irq[i];
1509 	kpc->max_gpios_level_type = level_line * KEEMBAY_GPIO_MAX_PER_IRQ;
1510 	kpc->max_gpios_edge_type = edge_line * KEEMBAY_GPIO_MAX_PER_IRQ;
1515 	return devm_gpiochip_add_data(kpc->dev, gc, kpc);
1518 static int keembay_build_groups(struct keembay_pinctrl *kpc)
1523 	kpc->ngroups = kpc->npins;
1524 	grp = devm_kcalloc(kpc->dev, kpc->ngroups, sizeof(*grp), GFP_KERNEL);
1529 	for (i = 0; i < kpc->ngroups; i++) {
1535 		pinctrl_generic_add_group(kpc->pctrl, kmb_grp->name,
1542 static int keembay_pinctrl_reg(struct keembay_pinctrl *kpc,  struct device *dev)
1547 	ret = of_property_read_u32(dev->of_node, "ngpios", &kpc->npins);
1550 	keembay_pinctrl_desc.npins = kpc->npins;
1552 	kpc->pctrl = devm_pinctrl_register(kpc->dev, &keembay_pinctrl_desc, kpc);
1554 	return PTR_ERR_OR_ZERO(kpc->pctrl);
1557 static int keembay_add_functions(struct keembay_pinctrl *kpc,
1563 	for (i = 0; i < kpc->nfuncs; i++) {
1569 		group_names = devm_kcalloc(kpc->dev, func->num_group_names,
1574 		for (j = 0; j < kpc->npins; j++) {
1588 	for (i = 0; i < kpc->nfuncs; i++) {
1589 		pinmux_generic_add_function(kpc->pctrl,
1599 static int keembay_build_functions(struct keembay_pinctrl *kpc)
1608 	kpc->nfuncs = 0;
1609 	keembay_funcs = kcalloc(kpc->npins * 8, sizeof(*keembay_funcs), GFP_KERNEL);
1614 	for (i = 0; i < kpc->npins; i++) {
1634 				kpc->nfuncs++;
1640 	new_funcs = krealloc(keembay_funcs, kpc->nfuncs * sizeof(*new_funcs), GFP_KERNEL);
1646 	return keembay_add_functions(kpc, new_funcs);
1662 	struct keembay_pinctrl *kpc;
1665 	kpc = devm_kzalloc(dev, sizeof(*kpc), GFP_KERNEL);
1666 	if (!kpc)
1669 	kpc->dev = dev;
1670 	kpc->soc = device_get_match_data(dev);
1672 	kpc->base0 = devm_platform_ioremap_resource(pdev, 0);
1673 	if (IS_ERR(kpc->base0))
1674 		return PTR_ERR(kpc->base0);
1676 	kpc->base1 = devm_platform_ioremap_resource(pdev, 1);
1677 	if (IS_ERR(kpc->base1))
1678 		return PTR_ERR(kpc->base1);
1680 	raw_spin_lock_init(&kpc->lock);
1682 	ret = keembay_pinctrl_reg(kpc, dev);
1686 	ret = keembay_build_groups(kpc);
1690 	ret = keembay_build_functions(kpc);
1694 	ret = keembay_gpiochip_probe(kpc, pdev);
1698 	platform_set_drvdata(pdev, kpc);