drivers/pinctrl/pinctrl-amd.c

42 	u32 pin_reg;
46 	pin_reg = readl(gpio_dev->base + offset * 4);
49 	if (pin_reg & BIT(OUTPUT_ENABLE_OFF))
58 	u32 pin_reg;
62 	pin_reg = readl(gpio_dev->base + offset * 4);
63 	pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
64 	writel(pin_reg, gpio_dev->base + offset * 4);
73 	u32 pin_reg;
78 	pin_reg = readl(gpio_dev->base + offset * 4);
79 	pin_reg |= BIT(OUTPUT_ENABLE_OFF);
81 		pin_reg |= BIT(OUTPUT_VALUE_OFF);
83 		pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
84 	writel(pin_reg, gpio_dev->base + offset * 4);
92 	u32 pin_reg;
97 	pin_reg = readl(gpio_dev->base + offset * 4);
100 	return !!(pin_reg & BIT(PIN_STS_OFF));
105 	u32 pin_reg;
110 	pin_reg = readl(gpio_dev->base + offset * 4);
112 		pin_reg |= BIT(OUTPUT_VALUE_OFF);
114 		pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
115 	writel(pin_reg, gpio_dev->base + offset * 4);
123 	u32 pin_reg;
128 		pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
129 		if (pin_reg & INTERNAL_GPIO0_DEBOUNCE)
133 	pin_reg = readl(gpio_dev->base + offset * 4);
136 		pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
137 		pin_reg &= ~DB_TMR_OUT_MASK;
149 			pin_reg |= 1;
150 			pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
151 			pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
154 			pin_reg |= time & DB_TMR_OUT_MASK;
155 			pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
156 			pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
159 			pin_reg |= time & DB_TMR_OUT_MASK;
160 			pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
161 			pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
164 			pin_reg |= time & DB_TMR_OUT_MASK;
165 			pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
166 			pin_reg |= BIT(DB_TMR_LARGE_OFF);
169 			pin_reg |= time & DB_TMR_OUT_MASK;
170 			pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
171 			pin_reg |= BIT(DB_TMR_LARGE_OFF);
173 			pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
177 		pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
178 		pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
179 		pin_reg &= ~DB_TMR_OUT_MASK;
180 		pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
182 	writel(pin_reg, gpio_dev->base + offset * 4);
190 	u32 pin_reg;
244 			pin_reg = readl(gpio_dev->base + i * 4);
247 			if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
248 				u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) &
255 				else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) &&
261 				if (pin_reg & BIT(LEVEL_TRIG_OFF))
266 				if (pin_reg & BIT(INTERRUPT_MASK_OFF))
271 				if (pin_reg & BIT(INTERRUPT_STS_OFF))
284 			if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3))
290 			if (pin_reg & BIT(WAKE_CNTRL_OFF_S3))
296 			if (pin_reg & BIT(WAKE_CNTRL_OFF_S4))
302 			if (pin_reg & BIT(WAKECNTRL_Z_OFF))
308 			if (pin_reg & BIT(WAKE_STS_OFF))
314 			if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
316 			} else if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) {
322 			if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) {
324 				if (pin_reg & BIT(OUTPUT_VALUE_OFF))
330 				if (pin_reg & BIT(PIN_STS_OFF))
337 			db_cntrl = (DB_CNTRl_MASK << DB_CNTRL_OFF) & pin_reg;
339 				tmr_out_unit = pin_reg & BIT(DB_TMR_OUT_UNIT_OFF);
340 				tmr_large = pin_reg & BIT(DB_TMR_LARGE_OFF);
341 				time = pin_reg & DB_TMR_OUT_MASK;
364 			seq_printf(s, "0x%x\n", pin_reg);
374 	u32 pin_reg;
382 	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
383 	pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
384 	pin_reg |= BIT(INTERRUPT_MASK_OFF);
385 	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
391 	u32 pin_reg;
397 	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
398 	pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
399 	pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
400 	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
408 	u32 pin_reg;
414 	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
415 	pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
416 	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
422 	u32 pin_reg;
428 	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
429 	pin_reg |= BIT(INTERRUPT_MASK_OFF);
430 	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
436 	u32 pin_reg;
444 	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
447 		pin_reg |= wake_mask;
449 		pin_reg &= ~wake_mask;
451 	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
483 	u32 pin_reg, pin_reg_irq_en, mask;
489 	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
493 		pin_reg &= ~BIT(LEVEL_TRIG_OFF);
494 		pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
495 		pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
500 		pin_reg &= ~BIT(LEVEL_TRIG_OFF);
501 		pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
502 		pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
507 		pin_reg &= ~BIT(LEVEL_TRIG_OFF);
508 		pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
509 		pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
514 		pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
515 		pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
516 		pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
521 		pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
522 		pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
523 		pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
535 	pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
552 	pin_reg_irq_en = pin_reg;
558 	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
724 	u32 pin_reg;
731 	pin_reg = readl(gpio_dev->base + pin*4);
735 		arg = pin_reg & DB_TMR_OUT_MASK;
739 		arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0);
743 		arg = (pin_reg >> PULL_UP_ENABLE_OFF) & BIT(0);
747 		arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK;
767 	u32 pin_reg;
776 		pin_reg = readl(gpio_dev->base + pin*4);
784 			pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
785 			pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF;
789 			pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);
790 			pin_reg |= (arg & BIT(0)) << PULL_UP_ENABLE_OFF;
794 			pin_reg &= ~(DRV_STRENGTH_SEL_MASK
796 			pin_reg |= (arg & DRV_STRENGTH_SEL_MASK)
806 		writel(pin_reg, gpio_dev->base + pin*4);
869 	u32 pin_reg, mask;
884 		pin_reg = readl(gpio_dev->base + pin * 4);
885 		pin_reg &= ~mask;
886 		writel(pin_reg, gpio_dev->base + pin * 4);