pinctrl/nuvoton/pinctrl-wpcm450.c

51 	struct wpcm450_pinctrl	*pctrl;
129 	struct wpcm450_pinctrl *pctrl = gpio->pctrl;
137 	raw_spin_lock_irqsave(&pctrl->lock, flags);
138 	iowrite32(BIT(bit), pctrl->gpio_base + WPCM450_GPEVST);
139 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
146 	struct wpcm450_pinctrl *pctrl = gpio->pctrl;
155 	raw_spin_lock_irqsave(&pctrl->lock, flags);
156 	even = ioread32(pctrl->gpio_base + WPCM450_GPEVEN);
158 	iowrite32(even, pctrl->gpio_base + WPCM450_GPEVEN);
159 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
168 	struct wpcm450_pinctrl *pctrl = gpio->pctrl;
179 	raw_spin_lock_irqsave(&pctrl->lock, flags);
180 	even = ioread32(pctrl->gpio_base + WPCM450_GPEVEN);
182 	iowrite32(even, pctrl->gpio_base + WPCM450_GPEVEN);
183 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
195 	void __iomem *reg = gpio->pctrl->gpio_base + gpio->bank->datain;
199 	raw_spin_lock_irqsave(&gpio->pctrl->lock, flags);
201 	raw_spin_unlock_irqrestore(&gpio->pctrl->lock, flags);
215 	struct wpcm450_pinctrl *pctrl = gpio->pctrl;
228 			raw_spin_lock_irqsave(&pctrl->lock, flags);
229 			evpol = ioread32(pctrl->gpio_base + WPCM450_GPEVPOL);
231 			iowrite32(evpol, pctrl->gpio_base + WPCM450_GPEVPOL);
232 			raw_spin_unlock_irqrestore(&pctrl->lock, flags);
241 	struct wpcm450_pinctrl *pctrl = gpio->pctrl;
253 	raw_spin_lock_irqsave(&pctrl->lock, flags);
254 	evtype = ioread32(pctrl->gpio_base + WPCM450_GPEVTYPE);
255 	evpol = ioread32(pctrl->gpio_base + WPCM450_GPEVPOL);
256 	__assign_bit(bit, &pctrl->both_edges, 0);
276 		__assign_bit(bit, &pctrl->both_edges, 1);
281 	iowrite32(evtype, pctrl->gpio_base + WPCM450_GPEVTYPE);
282 	iowrite32(evpol, pctrl->gpio_base + WPCM450_GPEVPOL);
285 	iowrite32(BIT(bit), pctrl->gpio_base + WPCM450_GPEVST);
287 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
308 	struct wpcm450_pinctrl *pctrl = gpio->pctrl;
317 	raw_spin_lock_irqsave(&pctrl->lock, flags);
319 	pending = ioread32(pctrl->gpio_base + WPCM450_GPEVST);
320 	pending &= ioread32(pctrl->gpio_base + WPCM450_GPEVEN);
323 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
325 	if (pending & pctrl->both_edges)
326 		wpcm450_gpio_fix_evpol(gpio, pending & pctrl->both_edges);
900 	struct wpcm450_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
902 	wpcm450_setfunc(pctrl->gcr_regmap, wpcm450_groups[group].pins,
925 	struct wpcm450_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
937 		raw_spin_lock_irqsave(&pctrl->lock, flags);
938 		reg = ioread32(pctrl->gpio_base + WPCM450_GPEVDBNC);
939 		raw_spin_unlock_irqrestore(&pctrl->lock, flags);
948 static int wpcm450_config_set_one(struct wpcm450_pinctrl *pctrl,
965 		raw_spin_lock_irqsave(&pctrl->lock, flags);
966 		reg = ioread32(pctrl->gpio_base + WPCM450_GPEVDBNC);
968 		iowrite32(reg, pctrl->gpio_base + WPCM450_GPEVDBNC);
969 		raw_spin_unlock_irqrestore(&pctrl->lock, flags);
979 	struct wpcm450_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
983 		ret = wpcm450_config_set_one(pctrl, pin, *configs++);
1012 	return wpcm450_config_set_one(gpio->pctrl, offset, config);
1020 	return gpiochip_add_pin_range(&gpio->gc, dev_name(gpio->pctrl->dev),
1025 				 struct wpcm450_pinctrl *pctrl)
1031 	pctrl->gpio_base = devm_platform_ioremap_resource(pdev, 0);
1032 	if (IS_ERR(pctrl->gpio_base))
1033 		return dev_err_probe(dev, PTR_ERR(pctrl->gpio_base),
1058 		gpio = &pctrl->gpio_bank[reg];
1059 		gpio->pctrl = pctrl;
1064 		dat = pctrl->gpio_base + bank->datain;
1066 			set = pctrl->gpio_base + bank->dataout;
1067 			dirout = pctrl->gpio_base + bank->cfg0;
1116 	struct wpcm450_pinctrl *pctrl;
1119 	pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
1120 	if (!pctrl)
1123 	pctrl->dev = &pdev->dev;
1124 	raw_spin_lock_init(&pctrl->lock);
1125 	dev_set_drvdata(dev, pctrl);
1127 	pctrl->gcr_regmap =
1129 	if (IS_ERR(pctrl->gcr_regmap))
1130 		return dev_err_probe(dev, PTR_ERR(pctrl->gcr_regmap),
1133 	pctrl->pctldev = devm_pinctrl_register(dev,
1134 					       &wpcm450_pinctrl_desc, pctrl);
1135 	if (IS_ERR(pctrl->pctldev))
1136 		return dev_err_probe(dev, PTR_ERR(pctrl->pctldev),
1139 	ret = wpcm450_gpio_register(pdev, pctrl);