pinctrl/intel/pinctrl-baytrail.c

91  * This is the function value most pins have for GPIO muxing. If the value
93  * pin control implementation will set the muxing value to default GPIO if it
601 		u32 value;
610 		value = readl(padcfg0);
611 		value &= ~BYT_PIN_MUX;
612 		value |= func;
613 		writel(value, padcfg0);
627 		u32 value;
636 		value = readl(padcfg0);
637 		value &= ~BYT_PIN_MUX;
638 		value |= func[i];
639 		writel(value, padcfg0);
678 	u32 value;
682 	value = readl(reg);
685 	if (!(value & BYT_DIRECT_IRQ_EN))
686 		value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
688 	writel(value, reg);
697 	u32 value, gpio_mux;
707 	 * configured correctly we allow changing the mux value from
710 	value = readl(reg) & BYT_PIN_MUX;
712 	if (gpio_mux == value)
715 	value = readl(reg) & ~BYT_PIN_MUX;
716 	value |= gpio_mux;
717 	writel(value, reg);
757 	u32 value;
761 	value = readl(val_reg);
762 	value &= ~BYT_DIR_MASK;
764 		value |= BYT_OUTPUT_EN;
768 	writel(value, val_reg);
806 	case 1: /* Set default strength value in case none is given */
829 	u32 value;
831 	value = readl(reg);
832 	if (!(value & BYT_INPUT_EN))
839 	value &= ~BYT_INPUT_EN;
840 	writel(value, reg);
1047 static void byt_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
1060 	if (value)
1070 	u32 value;
1077 		value = readl(reg);
1079 	if (!(value & BYT_OUTPUT_EN))
1081 	if (!(value & BYT_INPUT_EN))
1110 				     unsigned int offset, int value)
1122 	if (value)
1268 	u32 value;
1278 	value = readl(reg);
1282 		value |= BYT_TRIG_LVL;
1285 		value |= BYT_TRIG_POS;
1288 		value |= BYT_TRIG_LVL;
1291 		value |= BYT_TRIG_NEG;
1294 		value |= (BYT_TRIG_NEG | BYT_TRIG_POS);
1298 	writel(value, reg);
1306 	u32 value;
1314 	value = readl(reg);
1316 	WARN(value & BYT_DIRECT_IRQ_EN,
1322 	value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG |
1325 	value |= BYT_GLITCH_FILTER_EN | BYT_GLITCH_F_SLOW_CLK |
1328 	writel(value, reg);
1402 	 * 2. The TRIG_LVL bit *must* be set, so that the GPIO's input value is directly
1426 	u32 value;
1443 		value = readl(reg);
1444 		if (value & BYT_DIRECT_IRQ_EN) {
1445 			if (byt_direct_irq_sanity_check(vg, i, value)) {
1448 				value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS |
1450 				writel(value, reg);
1452 		} else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) {
1463 	u32 base, value;
1477 		value = readl(reg);
1478 		if (value)
1481 				base / 32, value);
1636 		u32 value;
1644 		value = readl(reg) & BYT_CONF0_RESTORE_MASK;
1645 		vg->context.pads[i].conf0 = value;
1652 		value = readl(reg) & BYT_VAL_RESTORE_MASK;
1653 		vg->context.pads[i].val = value;
1668 		u32 value;
1676 		value = readl(reg);
1677 		if ((value & BYT_CONF0_RESTORE_MASK) !=
1679 			value &= ~BYT_CONF0_RESTORE_MASK;
1680 			value |= vg->context.pads[i].conf0;
1681 			writel(value, reg);
1682 			dev_info(dev, "restored pin %d CONF0 %#08x", i, value);
1690 		value = readl(reg);
1691 		if ((value & BYT_VAL_RESTORE_MASK) !=
1695 			v = value & ~BYT_VAL_RESTORE_MASK;
1697 			if (v != value) {