Lines Matching refs:pc
247 static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg)
249 return readl(pc->base + reg);
252 static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg,
255 writel(val, pc->base + reg);
258 static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg,
262 return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1;
266 static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc,
270 bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit)));
274 struct bcm2835_pinctrl *pc, unsigned pin)
276 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
279 dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin,
286 struct bcm2835_pinctrl *pc, unsigned pin,
293 spin_lock_irqsave(&pc->fsel_lock, flags);
294 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
297 dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin,
308 dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin,
310 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
316 dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin,
318 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
321 spin_unlock_irqrestore(&pc->fsel_lock, flags);
326 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
328 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
334 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
336 return bcm2835_gpio_get_bit(pc, GPLEV0, offset);
341 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
342 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
356 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
358 bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
364 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
366 bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
367 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_OUT);
417 static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
424 events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
426 events &= pc->enabled_irq_map[bank];
429 generic_handle_domain_irq(pc->gpio_chip.irq.domain,
437 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
456 bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff);
459 bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000);
460 bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff);
463 bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000);
475 static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
480 value = bcm2835_gpio_rd(pc, reg);
485 bcm2835_gpio_wr(pc, reg, value);
489 static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
492 switch (pc->irq_type[offset]) {
494 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
498 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
502 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
503 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
507 __bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable);
511 __bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable);
519 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
527 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
528 set_bit(offset, &pc->enabled_irq_map[bank]);
529 bcm2835_gpio_irq_config(pc, gpio, true);
530 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
536 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
542 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
543 bcm2835_gpio_irq_config(pc, gpio, false);
545 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
546 clear_bit(offset, &pc->enabled_irq_map[bank]);
547 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
552 static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc,
562 pc->irq_type[offset] = type;
572 static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc,
577 if (pc->irq_type[offset] != type) {
578 bcm2835_gpio_irq_config(pc, offset, false);
579 pc->irq_type[offset] = type;
584 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
586 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
587 bcm2835_gpio_irq_config(pc, offset, false);
588 pc->irq_type[offset] = type;
589 } else if (pc->irq_type[offset] != type) {
590 bcm2835_gpio_irq_config(pc, offset, false);
591 pc->irq_type[offset] = type;
592 bcm2835_gpio_irq_config(pc, offset, true);
597 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
599 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
600 bcm2835_gpio_irq_config(pc, offset, false);
601 pc->irq_type[offset] = type;
602 } else if (pc->irq_type[offset] != type) {
603 bcm2835_gpio_irq_config(pc, offset, false);
604 pc->irq_type[offset] = type;
605 bcm2835_gpio_irq_config(pc, offset, true);
610 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) {
612 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
613 bcm2835_gpio_irq_config(pc, offset, true);
614 pc->irq_type[offset] = type;
615 } else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) {
617 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
618 bcm2835_gpio_irq_config(pc, offset, true);
619 pc->irq_type[offset] = type;
620 } else if (pc->irq_type[offset] != type) {
621 bcm2835_gpio_irq_config(pc, offset, false);
622 pc->irq_type[offset] = type;
623 bcm2835_gpio_irq_config(pc, offset, true);
629 if (pc->irq_type[offset] != type) {
630 bcm2835_gpio_irq_config(pc, offset, false);
631 pc->irq_type[offset] = type;
632 bcm2835_gpio_irq_config(pc, offset, true);
645 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
652 raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
654 if (test_bit(offset, &pc->enabled_irq_map[bank]))
655 ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type);
657 ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type);
664 raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
672 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
675 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
681 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
686 if (!pc->wake_irq)
699 ret = enable_irq_wake(pc->wake_irq[irqgroup]);
701 ret = disable_irq_wake(pc->wake_irq[irqgroup]);
743 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
744 struct gpio_chip *chip = &pc->gpio_chip;
745 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
747 int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset);
752 irq, irq_type_names[pc->irq_type[offset]]);
767 static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc,
774 dev_err(pc->dev, "%pOF: invalid brcm,function %d\n", np, fnum);
786 static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc,
794 dev_err(pc->dev, "%pOF: invalid brcm,pull %d\n", np, pull);
816 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
831 dev_err(pc->dev, "%pOF: missing brcm,pins property\n", np);
839 dev_err(pc->dev,
850 dev_err(pc->dev,
857 dev_err(pc->dev,
877 if (pin >= pc->pctl_desc.npins) {
878 dev_err(pc->dev, "%pOF: invalid brcm,pins value %d\n",
889 err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin,
899 err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin,
928 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
931 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
962 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
964 bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector);
973 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
976 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
984 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
988 bcm2835_pinctrl_fsel_set(pc, offset, fsel);
1010 static void bcm2835_pull_config_set(struct bcm2835_pinctrl *pc,
1018 bcm2835_gpio_wr(pc, GPPUD, arg & 3);
1026 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
1028 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
1035 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1046 bcm2835_pull_config_set(pc, pin, arg);
1051 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_OFF);
1055 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_DOWN);
1059 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_UP);
1064 bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
1082 static void bcm2711_pull_config_set(struct bcm2835_pinctrl *pc,
1092 value = bcm2835_gpio_rd(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4));
1095 bcm2835_gpio_wr(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4), value);
1102 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1120 bcm2711_pull_config_set(pc, pin, arg);
1125 bcm2711_pull_config_set(pc, pin, BCM2711_PULL_NONE);
1128 bcm2711_pull_config_set(pc, pin, BCM2711_PULL_DOWN);
1131 bcm2711_pull_config_set(pc, pin, BCM2711_PULL_UP);
1136 bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
1222 struct bcm2835_pinctrl *pc;
1232 pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
1233 if (!pc)
1236 platform_set_drvdata(pdev, pc);
1237 pc->dev = dev;
1245 pc->base = devm_ioremap_resource(dev, &iomem);
1246 if (IS_ERR(pc->base))
1247 return PTR_ERR(pc->base);
1256 pc->gpio_chip = *pdata->gpio_chip;
1257 pc->gpio_chip.parent = dev;
1259 spin_lock_init(&pc->fsel_lock);
1265 bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0);
1266 bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0);
1267 bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0);
1268 bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0);
1269 bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0);
1270 bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0);
1273 events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4);
1275 bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
1277 raw_spin_lock_init(&pc->irq_lock[i]);
1280 pc->pctl_desc = *pdata->pctl_desc;
1281 pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc);
1282 if (IS_ERR(pc->pctl_dev)) {
1283 gpiochip_remove(&pc->gpio_chip);
1284 return PTR_ERR(pc->pctl_dev);
1287 pc->gpio_range = *pdata->gpio_range;
1288 pc->gpio_range.base = pc->gpio_chip.base;
1289 pc->gpio_range.gc = &pc->gpio_chip;
1290 pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
1292 girq = &pc->gpio_chip.irq;
1305 pc->wake_irq = devm_kcalloc(dev, BCM2835_NUM_IRQS,
1306 sizeof(*pc->wake_irq),
1308 if (!pc->wake_irq) {
1334 pc->wake_irq[i] = irq_of_parse_and_map(np, i +
1337 len = strlen(dev_name(pc->dev)) + 16;
1338 name = devm_kzalloc(pc->dev, len, GFP_KERNEL);
1344 snprintf(name, len, "%s:bank%d", dev_name(pc->dev), i);
1347 err = devm_request_irq(dev, pc->wake_irq[i],
1349 IRQF_SHARED, name, pc);
1352 pc->wake_irq[i]);
1358 err = gpiochip_add_data(&pc->gpio_chip, pc);
1367 pinctrl_remove_gpio_range(pc->pctl_dev, &pc->gpio_range);