pinctrl/actions/pinctrl-owl.c

69 static u32 owl_read_field(struct owl_pinctrl *pctrl, u32 reg,
74 	tmp = readl_relaxed(pctrl->base + reg);
80 static void owl_write_field(struct owl_pinctrl *pctrl, u32 reg, u32 arg,
88 	owl_update_bits(pctrl->base + reg, mask, (arg << bit));
93 	struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
95 	return pctrl->soc->ngroups;
101 	struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
103 	return pctrl->soc->groups[group].name;
111 	struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
113 	*pins = pctrl->soc->groups[group].pads;
114 	*num_pins = pctrl->soc->groups[group].npads;
123 	struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
125 	seq_printf(s, "%s", dev_name(pctrl->dev));
139 	struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
141 	return pctrl->soc->nfunctions;
147 	struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
149 	return pctrl->soc->functions[function].name;
157 	struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
159 	*groups = pctrl->soc->functions[function].groups;
160 	*num_groups = pctrl->soc->functions[function].ngroups;
196 	struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
201 	g = &pctrl->soc->groups[group];
206 	raw_spin_lock_irqsave(&pctrl->lock, flags);
208 	owl_update_bits(pctrl->base + g->mfpctl_reg, mask, val);
210 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
258 	struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
263 	info = &pctrl->soc->padinfo[pin];
269 	arg = owl_read_field(pctrl, reg, bit, width);
271 	if (!pctrl->soc->padctl_val2arg)
274 	ret = pctrl->soc->padctl_val2arg(info, param, &arg);
288 	struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
295 	info = &pctrl->soc->padinfo[pin];
305 		if (!pctrl->soc->padctl_arg2val)
308 		ret = pctrl->soc->padctl_arg2val(info, param, &arg);
312 		raw_spin_lock_irqsave(&pctrl->lock, flags);
314 		owl_write_field(pctrl, reg, arg, bit, width);
316 		raw_spin_unlock_irqrestore(&pctrl->lock, flags);
427 	struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
432 	g = &pctrl->soc->groups[group];
438 	arg = owl_read_field(pctrl, reg, bit, width);
455 	struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
461 	g = &pctrl->soc->groups[group];
476 		raw_spin_lock_irqsave(&pctrl->lock, flags);
478 		owl_write_field(pctrl, reg, arg, bit, width);
480 		raw_spin_unlock_irqrestore(&pctrl->lock, flags);
502 owl_gpio_get_port(struct owl_pinctrl *pctrl, unsigned int *pin)
506 	for (i = 0; i < pctrl->soc->nports; i++) {
507 		const struct owl_gpio_port *port = &pctrl->soc->ports[i];
536 	struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
541 	port = owl_gpio_get_port(pctrl, &offset);
545 	gpio_base = pctrl->base + port->offset;
551 	raw_spin_lock_irqsave(&pctrl->lock, flags);
553 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
560 	struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
565 	port = owl_gpio_get_port(pctrl, &offset);
569 	gpio_base = pctrl->base + port->offset;
571 	raw_spin_lock_irqsave(&pctrl->lock, flags);
577 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
582 	struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
588 	port = owl_gpio_get_port(pctrl, &offset);
592 	gpio_base = pctrl->base + port->offset;
594 	raw_spin_lock_irqsave(&pctrl->lock, flags);
596 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
603 	struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
608 	port = owl_gpio_get_port(pctrl, &offset);
612 	gpio_base = pctrl->base + port->offset;
614 	raw_spin_lock_irqsave(&pctrl->lock, flags);
616 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
621 	struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
626 	port = owl_gpio_get_port(pctrl, &offset);
630 	gpio_base = pctrl->base + port->offset;
632 	raw_spin_lock_irqsave(&pctrl->lock, flags);
635 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
643 	struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
648 	port = owl_gpio_get_port(pctrl, &offset);
652 	gpio_base = pctrl->base + port->offset;
654 	raw_spin_lock_irqsave(&pctrl->lock, flags);
658 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
663 static void irq_set_type(struct owl_pinctrl *pctrl, int gpio, unsigned int type)
678 		if (owl_gpio_get(&pctrl->chip, gpio))
704 	port = owl_gpio_get_port(pctrl, &gpio);
708 	gpio_base = pctrl->base + port->offset;
710 	raw_spin_lock_irqsave(&pctrl->lock, flags);
718 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
724 	struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
732 	port = owl_gpio_get_port(pctrl, &gpio);
736 	gpio_base = pctrl->base + port->offset;
738 	raw_spin_lock_irqsave(&pctrl->lock, flags);
748 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
756 	struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
764 	port = owl_gpio_get_port(pctrl, &gpio);
770 	gpio_base = pctrl->base + port->offset;
771 	raw_spin_lock_irqsave(&pctrl->lock, flags);
782 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
788 	struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
801 			irq_set_type(pctrl, hwirq, IRQ_TYPE_EDGE_FALLING);
803 			irq_set_type(pctrl, hwirq, IRQ_TYPE_EDGE_RISING);
806 	port = owl_gpio_get_port(pctrl, &gpio);
810 	gpio_base = pctrl->base + port->offset;
812 	raw_spin_lock_irqsave(&pctrl->lock, flags);
817 	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
823 	struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
830 	irq_set_type(pctrl, data->hwirq, type);
847 	struct owl_pinctrl *pctrl = irq_desc_get_handler_data(desc);
849 	struct irq_domain *domain = pctrl->chip.irq.domain;
858 	for (i = 0; i < pctrl->soc->nports; i++) {
859 		port = &pctrl->soc->ports[i];
860 		base = pctrl->base + port->offset;
863 		if (parent != pctrl->irq[i])
882 static int owl_gpio_init(struct owl_pinctrl *pctrl)
888 	chip = &pctrl->chip;
890 	chip->ngpio = pctrl->soc->ngpios;
891 	chip->label = dev_name(pctrl->dev);
892 	chip->parent = pctrl->dev;
900 	gpio_irq->parent_handler_data = pctrl;
901 	gpio_irq->num_parents = pctrl->num_irq;
902 	gpio_irq->parents = pctrl->irq;
904 	gpio_irq->map = devm_kcalloc(pctrl->dev, chip->ngpio,
909 	for (i = 0, offset = 0; i < pctrl->soc->nports; i++) {
910 		const struct owl_gpio_port *port = &pctrl->soc->ports[i];
918 	ret = gpiochip_add_data(&pctrl->chip, pctrl);
920 		dev_err(pctrl->dev, "failed to register gpiochip\n");
930 	struct owl_pinctrl *pctrl;
933 	pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
934 	if (!pctrl)
937 	pctrl->base = devm_platform_ioremap_resource(pdev, 0);
938 	if (IS_ERR(pctrl->base))
939 		return PTR_ERR(pctrl->base);
942 	pctrl->clk = devm_clk_get(&pdev->dev, NULL);
943 	if (IS_ERR(pctrl->clk)) {
945 		return PTR_ERR(pctrl->clk);
948 	ret = clk_prepare_enable(pctrl->clk);
954 	raw_spin_lock_init(&pctrl->lock);
960 	pctrl->chip.direction_input  = owl_gpio_direction_input;
961 	pctrl->chip.direction_output = owl_gpio_direction_output;
962 	pctrl->chip.get = owl_gpio_get;
963 	pctrl->chip.set = owl_gpio_set;
964 	pctrl->chip.request = owl_gpio_request;
965 	pctrl->chip.free = owl_gpio_free;
967 	pctrl->soc = soc_data;
968 	pctrl->dev = &pdev->dev;
970 	pctrl->pctrldev = devm_pinctrl_register(&pdev->dev,
971 					&owl_pinctrl_desc, pctrl);
972 	if (IS_ERR(pctrl->pctrldev)) {
974 		ret = PTR_ERR(pctrl->pctrldev);
982 	pctrl->num_irq = ret;
984 	pctrl->irq = devm_kcalloc(&pdev->dev, pctrl->num_irq,
985 					sizeof(*pctrl->irq), GFP_KERNEL);
986 	if (!pctrl->irq) {
991 	for (i = 0; i < pctrl->num_irq ; i++) {
995 		pctrl->irq[i] = ret;
998 	ret = owl_gpio_init(pctrl);
1002 	platform_set_drvdata(pdev, pctrl);
1007 	clk_disable_unprepare(pctrl->clk);