Lines Matching refs:writeb_relaxed
371 writeb_relaxed(RST_APPLI_SW, base + MIPHY_CONF_RESET);
374 writeb_relaxed(val, base + MIPHY_CONF_RESET);
376 writeb_relaxed(RST_APPLI_SW, base + MIPHY_CONF_RESET);
381 writeb_relaxed(val, base + MIPHY_CONTROL);
384 writeb_relaxed(val, base + MIPHY_CONTROL);
395 writeb_relaxed(0x1d, base + MIPHY_PLL_SPAREIN);
396 writeb_relaxed(pll_ratio->clk_ref, base + MIPHY_PLL_CLKREF_FREQ);
399 writeb_relaxed(pll_ratio->calset_1, base + MIPHY_PLL_CALSET_1);
400 writeb_relaxed(pll_ratio->calset_2, base + MIPHY_PLL_CALSET_2);
401 writeb_relaxed(pll_ratio->calset_3, base + MIPHY_PLL_CALSET_3);
402 writeb_relaxed(pll_ratio->calset_4, base + MIPHY_PLL_CALSET_4);
403 writeb_relaxed(pll_ratio->cal_ctrl, base + MIPHY_PLL_CALSET_CTRL);
405 writeb_relaxed(TX_SEL, base + MIPHY_BOUNDARY_SEL);
408 writeb_relaxed(val, base + MIPHY_TX_CAL_MAN);
415 writeb_relaxed(val, base + MIPHY_RX_CAL_OFFSET_CTRL);
418 writeb_relaxed(0x00, base + MIPHY_CONF);
419 writeb_relaxed(0x70, base + MIPHY_RX_LOCK_STEP);
420 writeb_relaxed(EN_FIRST_HALF, base + MIPHY_RX_SIGDET_SLEEP_OA);
421 writeb_relaxed(EN_FIRST_HALF, base + MIPHY_RX_SIGDET_SLEEP_SEL);
422 writeb_relaxed(EN_FIRST_HALF, base + MIPHY_RX_SIGDET_WAIT_SEL);
425 writeb_relaxed(val, base + MIPHY_RX_SIGDET_DATA_SEL);
439 writeb_relaxed(gen->bank, base + MIPHY_CONF);
440 writeb_relaxed(gen->speed, base + MIPHY_SPEED);
441 writeb_relaxed(gen->bias_boost_1, base + MIPHY_BIAS_BOOST_1);
442 writeb_relaxed(gen->bias_boost_2, base + MIPHY_BIAS_BOOST_2);
445 writeb_relaxed(gen->tx_ctrl_2, base + MIPHY_TX_CTRL_2);
446 writeb_relaxed(gen->tx_ctrl_3, base + MIPHY_TX_CTRL_3);
449 writeb_relaxed(gen->rx_buff_ctrl, base + MIPHY_RX_BUFFER_CTRL);
450 writeb_relaxed(gen->rx_vga_gain, base + MIPHY_RX_VGA_GAIN);
451 writeb_relaxed(gen->rx_equ_gain_1, base + MIPHY_RX_EQU_GAIN_1);
452 writeb_relaxed(gen->rx_equ_gain_2, base + MIPHY_RX_EQU_GAIN_2);
453 writeb_relaxed(gen->rx_equ_gain_3, base + MIPHY_RX_EQU_GAIN_3);
466 writeb_relaxed(gen->bank, base + MIPHY_CONF);
467 writeb_relaxed(gen->speed, base + MIPHY_SPEED);
468 writeb_relaxed(gen->bias_boost_1, base + MIPHY_BIAS_BOOST_1);
469 writeb_relaxed(gen->bias_boost_2, base + MIPHY_BIAS_BOOST_2);
472 writeb_relaxed(gen->tx_ctrl_1, base + MIPHY_TX_CTRL_1);
473 writeb_relaxed(gen->tx_ctrl_2, base + MIPHY_TX_CTRL_2);
474 writeb_relaxed(gen->tx_ctrl_3, base + MIPHY_TX_CTRL_3);
476 writeb_relaxed(gen->rx_k_gain, base + MIPHY_RX_K_GAIN);
479 writeb_relaxed(gen->rx_buff_ctrl, base + MIPHY_RX_BUFFER_CTRL);
480 writeb_relaxed(gen->rx_vga_gain, base + MIPHY_RX_VGA_GAIN);
481 writeb_relaxed(gen->rx_equ_gain_1, base + MIPHY_RX_EQU_GAIN_1);
482 writeb_relaxed(gen->rx_equ_gain_2, base + MIPHY_RX_EQU_GAIN_2);
503 writeb_relaxed(RST_PLL_SW | RST_COMP_SW, base + MIPHY_RESET);
505 writeb_relaxed(0x00, base + MIPHY_PLL_COMMON_MISC_2);
506 writeb_relaxed(pll_ratio->clk_ref, base + MIPHY_PLL_CLKREF_FREQ);
507 writeb_relaxed(COMP_START, base + MIPHY_COMP_FSM_1);
510 writeb_relaxed(RST_PLL_SW, base + MIPHY_RESET);
512 writeb_relaxed(0x00, base + MIPHY_RESET);
513 writeb_relaxed(START_ACT_FILT, base + MIPHY_PLL_COMMON_MISC_2);
514 writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1);
517 writeb_relaxed(0x00, base + MIPHY_COMP_POSTP);
531 writeb_relaxed(RST_APPLI_SW, base + MIPHY_CONF_RESET);
532 writeb_relaxed(0x00, base + MIPHY_CONF_RESET);
533 writeb_relaxed(RST_COMP_SW, base + MIPHY_RESET);
536 writeb_relaxed(val, base + MIPHY_RESET);
538 writeb_relaxed(0x00, base + MIPHY_PLL_COMMON_MISC_2);
539 writeb_relaxed(0x1e, base + MIPHY_PLL_CLKREF_FREQ);
540 writeb_relaxed(COMP_START, base + MIPHY_COMP_FSM_1);
541 writeb_relaxed(RST_PLL_SW, base + MIPHY_RESET);
542 writeb_relaxed(0x00, base + MIPHY_RESET);
543 writeb_relaxed(START_ACT_FILT, base + MIPHY_PLL_COMMON_MISC_2);
544 writeb_relaxed(0x00, base + MIPHY_CONF);
545 writeb_relaxed(0x00, base + MIPHY_BOUNDARY_1);
546 writeb_relaxed(0x00, base + MIPHY_TST_BIAS_BOOST_2);
547 writeb_relaxed(0x00, base + MIPHY_CONF);
548 writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1);
549 writeb_relaxed(0xa5, base + MIPHY_DEBUG_BUS);
550 writeb_relaxed(0x00, base + MIPHY_CONF);
565 writeb_relaxed(val, base + MIPHY_BOUNDARY_2);
569 writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL);
572 writeb_relaxed(val, base + MIPHY_CONF);
576 writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2);
577 writeb_relaxed(0x6c, base + MIPHY_PLL_SBR_3);
578 writeb_relaxed(0x81, base + MIPHY_PLL_SBR_4);
581 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
584 writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1);
587 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
603 writeb_relaxed(val, base + MIPHY_BOUNDARY_2);
607 writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL);
610 writeb_relaxed(val, base + MIPHY_CONF);
613 writeb_relaxed(0x69, base + MIPHY_PLL_SBR_3);
614 writeb_relaxed(0x21, base + MIPHY_PLL_SBR_4);
617 writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2);
618 writeb_relaxed(0x21, base + MIPHY_PLL_SBR_4);
621 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
624 writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1);
627 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
634 writeb_relaxed(0x02, miphy_phy->base + MIPHY_COMP_POSTP);
654 writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1);
657 writeb_relaxed(0x00, base + MIPHY_CONF_RESET);
669 writeb_relaxed(val, miphy_phy->base + MIPHY_CONTROL);
697 writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1);
700 writeb_relaxed(0x00, base + MIPHY_CONF_RESET);
730 writeb_relaxed(0x00, base + MIPHY_CONF);
733 writeb_relaxed(val, base + MIPHY_SPEED);
736 writeb_relaxed(0x1c, base + MIPHY_RX_LOCK_SETTINGS_OPT);
737 writeb_relaxed(0x51, base + MIPHY_RX_CAL_CTRL_1);
738 writeb_relaxed(0x70, base + MIPHY_RX_CAL_CTRL_2);
742 writeb_relaxed(val, base + MIPHY_RX_CAL_OFFSET_CTRL);
743 writeb_relaxed(0x22, base + MIPHY_RX_CAL_VGA_STEP);
744 writeb_relaxed(0x0e, base + MIPHY_RX_CAL_OPT_LENGTH);
747 writeb_relaxed(val, base + MIPHY_RX_BUFFER_CTRL);
748 writeb_relaxed(0x78, base + MIPHY_RX_EQU_GAIN_1);
749 writeb_relaxed(0x1b, base + MIPHY_SYNCHAR_CONTROL);
752 writeb_relaxed(0x02, base + MIPHY_COMP_POSTP);
757 writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL);
760 writeb_relaxed(0x00, base + MIPHY_BIAS_BOOST_1);
761 writeb_relaxed(0xa7, base + MIPHY_BIAS_BOOST_2);
764 writeb_relaxed(SSC_EN_SW, base + MIPHY_BOUNDARY_2);
767 writeb_relaxed(0x00, base + MIPHY_CONF);
770 writeb_relaxed(0x5a, base + MIPHY_PLL_SBR_3);
771 writeb_relaxed(0xa0, base + MIPHY_PLL_SBR_4);
774 writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2);
775 writeb_relaxed(0xa1, base + MIPHY_PLL_SBR_4);
778 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
781 writeb_relaxed(0x02, base + MIPHY_PLL_SBR_1);
784 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1);
787 writeb_relaxed(0xca, base + MIPHY_RX_K_GAIN);
791 writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1);
792 writeb_relaxed(0x29, base + MIPHY_RX_POWER_CTRL_1);
793 writeb_relaxed(0x1a, base + MIPHY_RX_POWER_CTRL_2);
966 writeb_relaxed(0x68, miphy_phy->pipebase + 0x104); /* Rise_0 */
967 writeb_relaxed(0x61, miphy_phy->pipebase + 0x105); /* Rise_1 */
968 writeb_relaxed(0x68, miphy_phy->pipebase + 0x108); /* Fall_0 */
969 writeb_relaxed(0x61, miphy_phy->pipebase + 0x109); /* Fall-1 */
970 writeb_relaxed(0x68, miphy_phy->pipebase + 0x10c); /* Threshold_0 */
971 writeb_relaxed(0x60, miphy_phy->pipebase + 0x10d); /* Threshold_1 */
998 writeb_relaxed(0x68, miphy_phy->pipebase + 0x23);
999 writeb_relaxed(0x61, miphy_phy->pipebase + 0x24);
1000 writeb_relaxed(0x68, miphy_phy->pipebase + 0x26);
1001 writeb_relaxed(0x61, miphy_phy->pipebase + 0x27);
1002 writeb_relaxed(0x18, miphy_phy->pipebase + 0x29);
1003 writeb_relaxed(0x61, miphy_phy->pipebase + 0x2a);
1006 writeb_relaxed(0X67, miphy_phy->pipebase + 0x68);
1007 writeb_relaxed(0x0d, miphy_phy->pipebase + 0x69);
1008 writeb_relaxed(0X67, miphy_phy->pipebase + 0x6a);
1009 writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6b);
1010 writeb_relaxed(0X67, miphy_phy->pipebase + 0x6c);
1011 writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6d);
1012 writeb_relaxed(0X67, miphy_phy->pipebase + 0x6e);
1013 writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6f);