Lines Matching defs:tx_ana_ctrl_reg_1
571 u16 tx_ana_ctrl_reg_1;
580 tx_ana_ctrl_reg_1 = readl(tcphy->base + TX_ANA_CTRL_REG_1);
582 tx_ana_ctrl_reg_1 |= AUXDA_POLARITY;
584 tx_ana_ctrl_reg_1 &= ~AUXDA_POLARITY;
585 writel(tx_ana_ctrl_reg_1, tcphy->base + TX_ANA_CTRL_REG_1);
591 u16 tx_ana_ctrl_reg_1;
612 tx_ana_ctrl_reg_1 = readl(tcphy->base + TX_ANA_CTRL_REG_1);
613 tx_ana_ctrl_reg_1 &= ~TXDA_CAL_LATCH_EN;
614 writel(tx_ana_ctrl_reg_1, tcphy->base + TX_ANA_CTRL_REG_1);
628 tx_ana_ctrl_reg_1 |= TXDA_CAL_LATCH_EN;
629 writel(tx_ana_ctrl_reg_1, tcphy->base + TX_ANA_CTRL_REG_1);
644 tx_ana_ctrl_reg_1 |= TXDA_UPHY_SUPPLY_EN;
645 writel(tx_ana_ctrl_reg_1, tcphy->base + TX_ANA_CTRL_REG_1);
647 tx_ana_ctrl_reg_1 |= TXDA_UPHY_SUPPLY_EN_DEL;
648 writel(tx_ana_ctrl_reg_1, tcphy->base + TX_ANA_CTRL_REG_1);
659 tx_ana_ctrl_reg_1 |= TXDA_DRV_LDO_EN;
660 writel(tx_ana_ctrl_reg_1, tcphy->base + TX_ANA_CTRL_REG_1);
662 tx_ana_ctrl_reg_1 |= TXDA_BGREF_EN;
663 writel(tx_ana_ctrl_reg_1, tcphy->base + TX_ANA_CTRL_REG_1);
686 tx_ana_ctrl_reg_1 |= TXDA_DP_AUX_EN;
687 tx_ana_ctrl_reg_1 |= TXDA_DECAP_EN;
688 tx_ana_ctrl_reg_1 &= ~TXDA_DRV_LDO_EN;
689 tx_ana_ctrl_reg_1 &= ~TXDA_BGREF_EN;
690 writel(tx_ana_ctrl_reg_1, tcphy->base + TX_ANA_CTRL_REG_1);
692 tx_ana_ctrl_reg_1 |= TXDA_DECAP_EN_DEL;
693 writel(tx_ana_ctrl_reg_1, tcphy->base + TX_ANA_CTRL_REG_1);