phy/rockchip/phy-rockchip-naneng-combphy.c

131 	int (*combphy_cfg)(struct rockchip_combphy_priv *priv);
151 static void rockchip_combphy_updatel(struct rockchip_combphy_priv *priv,
156 	temp = readl(priv->mmio + reg);
158 	writel(temp, priv->mmio + reg);
173 static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv)
175 	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
181 	regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val);
189 	struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
190 	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
194 	ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks);
196 		dev_err(priv->dev, "failed to enable clks\n");
200 	switch (priv->type) {
206 		if (priv->cfg->combphy_cfg)
207 			ret = priv->cfg->combphy_cfg(priv);
210 		dev_err(priv->dev, "incompatible PHY type\n");
216 		dev_err(priv->dev, "failed to init phy for phy type %x\n", priv->type);
220 	ret = reset_control_deassert(priv->phy_rst);
224 	if (priv->type == PHY_TYPE_USB3) {
226 						priv, val,
230 			dev_warn(priv->dev, "wait phy status ready timeout\n");
236 	clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
243 	struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
245 	clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
246 	reset_control_assert(priv->phy_rst);
259 	struct rockchip_combphy_priv *priv = dev_get_drvdata(dev);
266 	if (priv->type != PHY_NONE && priv->type != args->args[0])
268 			 args->args[0], priv->type);
270 	priv->type = args->args[0];
272 	return priv->phy;
275 static int rockchip_combphy_parse_dt(struct device *dev, struct rockchip_combphy_priv *priv)
279 	priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks);
280 	if (priv->num_clks < 1)
283 	priv->refclk = NULL;
284 	for (i = 0; i < priv->num_clks; i++) {
285 		if (!strncmp(priv->clks[i].id, "ref", 3)) {
286 			priv->refclk = priv->clks[i].clk;
291 	if (!priv->refclk) {
296 	priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-grf");
297 	if (IS_ERR(priv->pipe_grf)) {
299 		return PTR_ERR(priv->pipe_grf);
302 	priv->phy_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-phy-grf");
303 	if (IS_ERR(priv->phy_grf)) {
305 		return PTR_ERR(priv->phy_grf);
308 	priv->enable_ssc = device_property_present(dev, "rockchip,enable-ssc");
310 	priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk");
312 	priv->phy_rst = devm_reset_control_array_get_exclusive(dev);
313 	if (IS_ERR(priv->phy_rst))
314 		return dev_err_probe(dev, PTR_ERR(priv->phy_rst), "failed to get phy reset\n");
323 	struct rockchip_combphy_priv *priv;
334 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
335 	if (!priv)
338 	priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
339 	if (IS_ERR(priv->mmio)) {
340 		ret = PTR_ERR(priv->mmio);
345 	priv->id = -ENODEV;
348 			priv->id = id;
353 	priv->dev = dev;
354 	priv->type = PHY_NONE;
355 	priv->cfg = phy_cfg;
357 	ret = rockchip_combphy_parse_dt(dev, priv);
361 	ret = reset_control_assert(priv->phy_rst);
367 	priv->phy = devm_phy_create(dev, NULL, &rochchip_combphy_ops);
368 	if (IS_ERR(priv->phy)) {
370 		return PTR_ERR(priv->phy);
373 	dev_set_drvdata(dev, priv);
374 	phy_set_drvdata(priv->phy, priv);
381 static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
383 	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
387 	switch (priv->type) {
390 		rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
394 		rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
395 		rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
396 		rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
397 		rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
402 		rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
407 		val = readl(priv->mmio + PHYREG15);
409 		writel(val, priv->mmio + PHYREG15);
412 		rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
417 		writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
420 		rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
424 		writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
425 		writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
427 		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
428 		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
429 		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
430 		rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true);
435 		val = readl(priv->mmio + PHYREG15);
437 		writel(val, priv->mmio + PHYREG15);
444 		writel(val, priv->mmio + PHYREG7);
446 		rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true);
447 		rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true);
448 		rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true);
449 		rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true);
450 		rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
454 		rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
455 		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
456 		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
457 		rockchip_combphy_param_write(priv->phy_grf, &cfg->sgmii_mode_set, true);
461 		rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true);
462 		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true);
463 		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_rate_sel, true);
464 		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true);
465 		rockchip_combphy_param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true);
469 		dev_err(priv->dev, "incompatible PHY type\n");
473 	rate = clk_get_rate(priv->refclk);
477 		if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) {
480 			rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK,
483 			writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
488 		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
492 		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
493 		if (priv->type == PHY_TYPE_PCIE) {
496 			rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
500 			writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
503 			rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
506 			writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
507 			writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
508 		} else if (priv->type == PHY_TYPE_SATA) {
512 			rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32);
517 		dev_err(priv->dev, "unsupported rate: %lu\n", rate);
521 	if (priv->ext_refclk) {
522 		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
523 		if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
526 			rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13);
528 			val = readl(priv->mmio + PHYREG14);
530 			writel(val, priv->mmio + PHYREG14);
534 	if (priv->enable_ssc) {
535 		val = readl(priv->mmio + PHYREG8);
537 		writel(val, priv->mmio + PHYREG8);
587 static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
589 	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
593 	switch (priv->type) {
595 		rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
596 		rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
597 		rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
598 		rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
599 		switch (priv->id) {
601 			rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_pcie1l0_sel, true);
604 			rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_pcie1l1_sel, true);
610 		rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
615 		val = readl(priv->mmio + PHYREG15);
617 		writel(val, priv->mmio + PHYREG15);
620 		rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
625 		writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
628 		rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
632 		writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
633 		writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
635 		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
636 		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
637 		rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true);
641 		val = readl(priv->mmio + PHYREG15);
643 		writel(val, priv->mmio + PHYREG15);
650 		writel(val, priv->mmio + PHYREG7);
652 		rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true);
653 		rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true);
654 		rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true);
655 		rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true);
656 		rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
657 		rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true);
662 		dev_err(priv->dev, "incompatible PHY type\n");
666 	rate = clk_get_rate(priv->refclk);
670 		if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) {
673 			rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK,
676 			writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
681 		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
684 		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
685 		if (priv->type == PHY_TYPE_PCIE) {
688 			rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
692 			writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
695 			writel(PHYREG27_RX_TRIM_RK3588, priv->mmio + PHYREG27);
698 			writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
699 		} else if (priv->type == PHY_TYPE_SATA) {
703 			rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32);
707 		dev_err(priv->dev, "Unsupported rate: %lu\n", rate);
711 	if (priv->ext_refclk) {
712 		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
713 		if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
716 			rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13);
718 			val = readl(priv->mmio + PHYREG14);
720 			writel(val, priv->mmio + PHYREG14);
724 	if (priv->enable_ssc) {
725 		val = readl(priv->mmio + PHYREG8);
727 		writel(val, priv->mmio + PHYREG8);