phy/renesas/r8a779f0-ether-serdes.c

37 	struct r8a779f0_eth_serdes_channel channel[R8A779F0_ETH_SERDES_NUM];
53 r8a779f0_eth_serdes_reg_wait(struct r8a779f0_eth_serdes_channel *channel,
59 	iowrite32(bank, channel->addr + R8A779F0_ETH_SERDES_BANK_SELECT);
61 	ret = readl_poll_timeout_atomic(channel->addr + offs, val,
65 		dev_dbg(&channel->phy->dev,
67 			 __func__, channel->index, offs, bank, mask, expected);
75 	struct r8a779f0_eth_serdes_channel *channel;
79 		channel = &dd->channel[i];
80 		ret = r8a779f0_eth_serdes_reg_wait(channel, 0x026c, 0x180, BIT(0), 0x01);
91 r8a779f0_eth_serdes_common_setting(struct r8a779f0_eth_serdes_channel *channel)
93 	struct r8a779f0_eth_serdes_drv_data *dd = channel->dd;
95 	switch (channel->phy_interface) {
109 r8a779f0_eth_serdes_chan_setting(struct r8a779f0_eth_serdes_channel *channel)
113 	switch (channel->phy_interface) {
115 		r8a779f0_eth_serdes_write32(channel->addr, 0x0000, 0x380, 0x2000);
116 		r8a779f0_eth_serdes_write32(channel->addr, 0x01c0, 0x180, 0x0011);
117 		r8a779f0_eth_serdes_write32(channel->addr, 0x0248, 0x180, 0x0540);
118 		r8a779f0_eth_serdes_write32(channel->addr, 0x0258, 0x180, 0x0015);
119 		r8a779f0_eth_serdes_write32(channel->addr, 0x0144, 0x180, 0x0100);
120 		r8a779f0_eth_serdes_write32(channel->addr, 0x01a0, 0x180, 0x0000);
121 		r8a779f0_eth_serdes_write32(channel->addr, 0x00d0, 0x180, 0x0002);
122 		r8a779f0_eth_serdes_write32(channel->addr, 0x0150, 0x180, 0x0003);
123 		r8a779f0_eth_serdes_write32(channel->addr, 0x00c8, 0x180, 0x0100);
124 		r8a779f0_eth_serdes_write32(channel->addr, 0x0148, 0x180, 0x0100);
125 		r8a779f0_eth_serdes_write32(channel->addr, 0x0174, 0x180, 0x0000);
126 		r8a779f0_eth_serdes_write32(channel->addr, 0x0160, 0x180, 0x0007);
127 		r8a779f0_eth_serdes_write32(channel->addr, 0x01ac, 0x180, 0x0000);
128 		r8a779f0_eth_serdes_write32(channel->addr, 0x00c4, 0x180, 0x0310);
129 		r8a779f0_eth_serdes_write32(channel->addr, 0x00c8, 0x180, 0x0101);
130 		ret = r8a779f0_eth_serdes_reg_wait(channel, 0x00c8, 0x0180, BIT(0), 0);
134 		r8a779f0_eth_serdes_write32(channel->addr, 0x0148, 0x180, 0x0101);
135 		ret = r8a779f0_eth_serdes_reg_wait(channel, 0x0148, 0x0180, BIT(0), 0);
139 		r8a779f0_eth_serdes_write32(channel->addr, 0x00c4, 0x180, 0x1310);
140 		r8a779f0_eth_serdes_write32(channel->addr, 0x00d8, 0x180, 0x1800);
141 		r8a779f0_eth_serdes_write32(channel->addr, 0x00dc, 0x180, 0x0000);
142 		r8a779f0_eth_serdes_write32(channel->addr, 0x001c, 0x300, 0x0001);
143 		r8a779f0_eth_serdes_write32(channel->addr, 0x0000, 0x380, 0x2100);
144 		ret = r8a779f0_eth_serdes_reg_wait(channel, 0x0000, 0x0380, BIT(8), 0);
148 		if (channel->speed == 1000)
149 			r8a779f0_eth_serdes_write32(channel->addr, 0x0000, 0x1f00, 0x0140);
150 		else if (channel->speed == 100)
151 			r8a779f0_eth_serdes_write32(channel->addr, 0x0000, 0x1f00, 0x2100);
154 		r8a779f0_eth_serdes_write32(channel->addr, 0x0004, 0x1f80, 0x0005);
155 		r8a779f0_eth_serdes_write32(channel->addr, 0x0028, 0x1f80, 0x07a1);
156 		r8a779f0_eth_serdes_write32(channel->addr, 0x0000, 0x1f80, 0x0208);
166 r8a779f0_eth_serdes_chan_speed(struct r8a779f0_eth_serdes_channel *channel)
170 	switch (channel->phy_interface) {
173 		if (channel->speed == 1000)
174 			r8a779f0_eth_serdes_write32(channel->addr, 0x0000, 0x1f00, 0x1140);
175 		else if (channel->speed == 100)
176 			r8a779f0_eth_serdes_write32(channel->addr, 0x0000, 0x1f00, 0x3100);
177 		ret = r8a779f0_eth_serdes_reg_wait(channel, 0x0008, 0x1f80, BIT(0), 1);
180 		r8a779f0_eth_serdes_write32(channel->addr, 0x0008, 0x1f80, 0x0000);
190 static int r8a779f0_eth_serdes_monitor_linkup(struct r8a779f0_eth_serdes_channel *channel)
195 		ret = r8a779f0_eth_serdes_reg_wait(channel, 0x0004, 0x300,
201 		r8a779f0_eth_serdes_write32(channel->addr, 0x0144, 0x180, 0x0100);
203 		r8a779f0_eth_serdes_write32(channel->addr, 0x0144, 0x180, 0x0000);
209 static int r8a779f0_eth_serdes_hw_init(struct r8a779f0_eth_serdes_channel *channel)
211 	struct r8a779f0_eth_serdes_drv_data *dd = channel->dd;
226 		ret = r8a779f0_eth_serdes_reg_wait(&dd->channel[i], 0x0000,
233 		r8a779f0_eth_serdes_write32(dd->channel[i].addr, 0x03d4, 0x380, 0x0443);
235 	ret = r8a779f0_eth_serdes_common_setting(channel);
240 		r8a779f0_eth_serdes_write32(dd->channel[i].addr, 0x03d0, 0x380, 0x0001);
249 	return r8a779f0_eth_serdes_reg_wait(&dd->channel[0], 0x0000, 0x380, BIT(15), 0);
254 	struct r8a779f0_eth_serdes_channel *channel = phy_get_drvdata(p);
257 	ret = r8a779f0_eth_serdes_hw_init(channel);
259 		channel->dd->initialized = true;
266 	struct r8a779f0_eth_serdes_channel *channel = phy_get_drvdata(p);
268 	channel->dd->initialized = false;
274 *channel)
278 	ret = r8a779f0_eth_serdes_chan_setting(channel);
282 	ret = r8a779f0_eth_serdes_chan_speed(channel);
286 	r8a779f0_eth_serdes_write32(channel->addr, 0x03c0, 0x380, 0x0000);
288 	r8a779f0_eth_serdes_write32(channel->addr, 0x03d0, 0x380, 0x0000);
290 	return r8a779f0_eth_serdes_monitor_linkup(channel);
295 	struct r8a779f0_eth_serdes_channel *channel = phy_get_drvdata(p);
297 	return r8a779f0_eth_serdes_hw_init_late(channel);
303 	struct r8a779f0_eth_serdes_channel *channel = phy_get_drvdata(p);
312 		channel->phy_interface = submode;
321 	struct r8a779f0_eth_serdes_channel *channel = phy_get_drvdata(p);
323 	channel->speed = speed;
344 	return dd->channel[args->args[0]].phy;
374 		struct r8a779f0_eth_serdes_channel *channel = &dd->channel[i];
376 		channel->phy = devm_phy_create(&pdev->dev, NULL,
378 		if (IS_ERR(channel->phy))
379 			return PTR_ERR(channel->phy);
380 		channel->addr = dd->addr + R8A779F0_ETH_SERDES_OFFSET * i;
381 		channel->dd = dd;
382 		channel->index = i;
383 		phy_set_drvdata(channel->phy, channel);