Lines Matching refs:priv

50 static int qcom_ssphy_do_reset(struct ssphy_priv *priv)
54 if (!priv->reset_com) {
55 qcom_ssphy_updatel(priv->base + PHY_CTRL1, PHY_RESET,
58 qcom_ssphy_updatel(priv->base + PHY_CTRL1, PHY_RESET, 0);
60 ret = reset_control_assert(priv->reset_com);
62 dev_err(priv->dev, "Failed to assert reset com\n");
66 ret = reset_control_assert(priv->reset_phy);
68 dev_err(priv->dev, "Failed to assert reset phy\n");
74 ret = reset_control_deassert(priv->reset_com);
76 dev_err(priv->dev, "Failed to deassert reset com\n");
80 ret = reset_control_deassert(priv->reset_phy);
82 dev_err(priv->dev, "Failed to deassert reset phy\n");
92 struct ssphy_priv *priv = phy_get_drvdata(phy);
95 ret = regulator_bulk_enable(NUM_BULK_REGS, priv->regs);
99 ret = clk_bulk_prepare_enable(NUM_BULK_CLKS, priv->clks);
103 ret = qcom_ssphy_do_reset(priv);
107 writeb(SWI_PCS_CLK_SEL, priv->base + PHY_CTRL0);
108 qcom_ssphy_updatel(priv->base + PHY_CTRL4, LANE0_PWR_ON, LANE0_PWR_ON);
109 qcom_ssphy_updatel(priv->base + PHY_CTRL2, REF_PHY_EN, REF_PHY_EN);
110 qcom_ssphy_updatel(priv->base + PHY_CTRL4, TST_PWR_DOWN, 0);
114 clk_bulk_disable_unprepare(NUM_BULK_CLKS, priv->clks);
116 regulator_bulk_disable(NUM_BULK_REGS, priv->regs);
123 struct ssphy_priv *priv = phy_get_drvdata(phy);
125 qcom_ssphy_updatel(priv->base + PHY_CTRL4, LANE0_PWR_ON, 0);
126 qcom_ssphy_updatel(priv->base + PHY_CTRL2, REF_PHY_EN, 0);
127 qcom_ssphy_updatel(priv->base + PHY_CTRL4, TST_PWR_DOWN, TST_PWR_DOWN);
129 clk_bulk_disable_unprepare(NUM_BULK_CLKS, priv->clks);
130 regulator_bulk_disable(NUM_BULK_REGS, priv->regs);
135 static int qcom_ssphy_init_clock(struct ssphy_priv *priv)
137 priv->clks[0].id = "ref";
138 priv->clks[1].id = "ahb";
139 priv->clks[2].id = "pipe";
141 return devm_clk_bulk_get(priv->dev, NUM_BULK_CLKS, priv->clks);
144 static int qcom_ssphy_init_regulator(struct ssphy_priv *priv)
148 priv->regs[0].supply = "vdd";
149 priv->regs[1].supply = "vdda1p8";
150 ret = devm_regulator_bulk_get(priv->dev, NUM_BULK_REGS, priv->regs);
153 dev_err(priv->dev, "Failed to get regulators\n");
160 static int qcom_ssphy_init_reset(struct ssphy_priv *priv)
162 priv->reset_com = devm_reset_control_get_optional_exclusive(priv->dev, "com");
163 if (IS_ERR(priv->reset_com)) {
164 dev_err(priv->dev, "Failed to get reset control com\n");
165 return PTR_ERR(priv->reset_com);
168 if (priv->reset_com) {
170 priv->reset_phy = devm_reset_control_get_exclusive(priv->dev, "phy");
171 if (IS_ERR(priv->reset_phy)) {
172 dev_err(priv->dev, "Failed to get reset control phy\n");
173 return PTR_ERR(priv->reset_phy);
190 struct ssphy_priv *priv;
194 priv = devm_kzalloc(dev, sizeof(struct ssphy_priv), GFP_KERNEL);
195 if (!priv)
198 priv->dev = dev;
199 priv->mode = PHY_MODE_INVALID;
201 priv->base = devm_platform_ioremap_resource(pdev, 0);
202 if (IS_ERR(priv->base))
203 return PTR_ERR(priv->base);
205 ret = qcom_ssphy_init_clock(priv);
209 ret = qcom_ssphy_init_reset(priv);
213 ret = qcom_ssphy_init_regulator(priv);
223 phy_set_drvdata(phy, priv);