phy/qualcomm/phy-qcom-pcie2.c

72 	u32 val;
75 	val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2);
76 	val &= ~BIT(1);
77 	writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2);
82 	val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2);
83 	val &= ~BIT(0);
84 	writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2);
87 	val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL3);
88 	val |= BIT(0);
89 	writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL3);
94 	val = readl(qphy->base + PCIE2_PHY_RESET_CTRL);
95 	val |= BIT(0);
96 	writel(val, qphy->base + PCIE2_PHY_RESET_CTRL);
99 	val = readl(qphy->base + PCIE20_PARF_PCS_SWING_CTRL1);
100 	val &= ~0x7f;
101 	val |= TX_AMP_VAL;
102 	writel(val, qphy->base + PCIE20_PARF_PCS_SWING_CTRL1);
104 	val = readl(qphy->base + PCIE20_PARF_PCS_SWING_CTRL2);
105 	val &= ~0x7f;
106 	val |= TX_AMP_VAL;
107 	writel(val, qphy->base + PCIE20_PARF_PCS_SWING_CTRL2);
110 	val = readl(qphy->base + PCIE20_PARF_PCS_DEEMPH1);
111 	val &= ~0x3f;
112 	val |= TX_DEEMPH_GEN2_6DB_VAL;
113 	writel(val, qphy->base + PCIE20_PARF_PCS_DEEMPH1);
115 	val = readl(qphy->base + PCIE20_PARF_PCS_DEEMPH2);
116 	val &= ~0x3f;
117 	val |= TX_DEEMPH_GEN2_3_5DB_VAL;
118 	writel(val, qphy->base + PCIE20_PARF_PCS_DEEMPH2);
120 	val = readl(qphy->base + PCIE20_PARF_PCS_DEEMPH3);
121 	val &= ~0x3f;
122 	val |= TX_DEEMPH_GEN1_VAL;
123 	writel(val, qphy->base + PCIE20_PARF_PCS_DEEMPH3);
126 	val = readl(qphy->base + PCIE20_PARF_CONFIGBITS);
127 	val &= ~0x7;
128 	val |= PHY_RX0_EQ_GEN2_VAL;
129 	writel(val, qphy->base + PCIE20_PARF_CONFIGBITS);
132 	val = readl(qphy->base + PCIE20_PARF_PHY_CTRL3);
133 	val &= ~0x1f;
134 	val |= PHY_TX0_TERM_OFFST_VAL;
135 	writel(val, qphy->base + PCIE20_PARF_PHY_CTRL3);
138 	val = readl(qphy->base + PCIE20_PARF_PCS_CTRL);
139 	val &= ~BIT(1);
140 	writel(val, qphy->base + PCIE20_PARF_PCS_CTRL);
143 	val = readl(qphy->base + PCIE2_PHY_RESET_CTRL);
144 	val &= ~BIT(0);
145 	writel(val, qphy->base + PCIE2_PHY_RESET_CTRL);
163 	ret = readl_poll_timeout(qphy->base + PCIE20_PARF_PHY_STTS, val,
164 				 !(val & BIT(0)), 1000, 10);
175 	u32 val;
177 	val = readl(qphy->base + PCIE2_PHY_RESET_CTRL);
178 	val |= BIT(0);
179 	writel(val, qphy->base + PCIE2_PHY_RESET_CTRL);