phy/marvell/phy-mvebu-cp110-comphy.c

340 	u32 val;
342 	regmap_read(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), &val);
343 	val &= ~MVEBU_COMPHY_CONF1_USB_PCIE;
344 	val |= MVEBU_COMPHY_CONF1_PWRUP;
345 	regmap_write(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), val);
348 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id));
349 	val &= ~(MVEBU_COMPHY_SERDES_CFG0_PU_PLL |
359 		val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0xe) |
363 		val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0xb) |
368 		val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0x8) |
373 		val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0x6) |
385 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id));
388 		regmap_read(priv->regmap, MVEBU_COMPHY_SD1_CTRL1, &val);
393 			val |= MVEBU_COMPHY_SD1_CTRL1_RXAUI0_EN;
397 			val |= MVEBU_COMPHY_SD1_CTRL1_RXAUI1_EN;
406 		regmap_write(priv->regmap, MVEBU_COMPHY_SD1_CTRL1, val);
410 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
411 	val &= ~(MVEBU_COMPHY_SERDES_CFG1_RESET |
414 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
417 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
418 	val |= MVEBU_COMPHY_SERDES_CFG1_RESET |
420 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
426 	regmap_read(priv->regmap, MVEBU_COMPHY_CONF6(lane->id), &val);
427 	val &= ~MVEBU_COMPHY_CONF6_40B;
428 	regmap_write(priv->regmap, MVEBU_COMPHY_CONF6(lane->id), val);
431 	val = readl(priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id));
432 	val &= ~MVEBU_COMPHY_MISC_CTRL0_REFCLK_SEL;
434 		val |= MVEBU_COMPHY_MISC_CTRL0_ICP_FORCE;
435 	writel(val, priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id));
438 	val = readl(priv->base + MVEBU_COMPHY_PWRPLL_CTRL(lane->id));
439 	val &= ~(MVEBU_COMPHY_PWRPLL_CTRL_RFREQ(0x1f) |
441 	val |= MVEBU_COMPHY_PWRPLL_CTRL_RFREQ(0x1) |
443 	writel(val, priv->base + MVEBU_COMPHY_PWRPLL_CTRL(lane->id));
445 	val = readl(priv->base + MVEBU_COMPHY_LOOPBACK(lane->id));
446 	val &= ~MVEBU_COMPHY_LOOPBACK_DBUS_WIDTH(0x7);
447 	val |= MVEBU_COMPHY_LOOPBACK_DBUS_WIDTH(0x1);
448 	writel(val, priv->base + MVEBU_COMPHY_LOOPBACK(lane->id));
456 	u32 val;
459 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id));
460 	val |= MVEBU_COMPHY_SERDES_CFG0_PU_PLL |
463 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id));
467 			   val,
468 			   val & (MVEBU_COMPHY_SERDES_STATUS0_RX_PLL_RDY |
471 	if (!(val & (MVEBU_COMPHY_SERDES_STATUS0_RX_PLL_RDY |
476 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
477 	val |= MVEBU_COMPHY_SERDES_CFG1_RX_INIT;
478 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
482 			   val, val & MVEBU_COMPHY_SERDES_STATUS0_RX_INIT,
484 	if (!(val & MVEBU_COMPHY_SERDES_STATUS0_RX_INIT))
487 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
488 	val &= ~MVEBU_COMPHY_SERDES_CFG1_RX_INIT;
489 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
498 	u32 val;
505 	val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));
506 	val &= ~MVEBU_COMPHY_RX_CTRL1_CLK8T_EN;
507 	val |= MVEBU_COMPHY_RX_CTRL1_RXCLK2X_SEL;
508 	writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));
510 	val = readl(priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));
511 	val &= ~MVEBU_COMPHY_DTL_CTRL_DTL_FLOOP_EN;
512 	writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));
514 	regmap_read(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), &val);
515 	val &= ~MVEBU_COMPHY_CONF1_USB_PCIE;
516 	val |= MVEBU_COMPHY_CONF1_PWRUP;
517 	regmap_write(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), val);
519 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));
520 	val &= ~MVEBU_COMPHY_GEN1_S0_TX_EMPH(0xf);
521 	val |= MVEBU_COMPHY_GEN1_S0_TX_EMPH(0x1);
522 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));
531 	u32 val;
538 	val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));
539 	val |= MVEBU_COMPHY_RX_CTRL1_RXCLK2X_SEL |
541 	writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));
543 	val = readl(priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));
544 	val |= MVEBU_COMPHY_DTL_CTRL_DTL_FLOOP_EN;
545 	writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));
547 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id));
548 	val |= MVEBU_COMPHY_SERDES_CFG2_DFE_EN;
549 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id));
551 	val = readl(priv->base + MVEBU_COMPHY_DFE_RES(lane->id));
552 	val |= MVEBU_COMPHY_DFE_RES_FORCE_GEN_TBL;
553 	writel(val, priv->base + MVEBU_COMPHY_DFE_RES(lane->id));
555 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));
556 	val &= ~MVEBU_COMPHY_GEN1_S0_TX_EMPH(0xf);
557 	val |= MVEBU_COMPHY_GEN1_S0_TX_EMPH(0xd);
558 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));
560 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S1(lane->id));
561 	val &= ~(MVEBU_COMPHY_GEN1_S1_RX_MUL_PI(0x7) |
563 	val |= MVEBU_COMPHY_GEN1_S1_RX_MUL_PI(0x1) |
566 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S1(lane->id));
568 	val = readl(priv->base + MVEBU_COMPHY_COEF(lane->id));
569 	val &= ~(MVEBU_COMPHY_COEF_DFE_EN | MVEBU_COMPHY_COEF_DFE_CTRL);
570 	writel(val, priv->base + MVEBU_COMPHY_COEF(lane->id));
572 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S4(lane->id));
573 	val &= ~MVEBU_COMPHY_GEN1_S4_DFE_RES(0x3);
574 	val |= MVEBU_COMPHY_GEN1_S4_DFE_RES(0x1);
575 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S4(lane->id));
584 	u32 val;
591 	val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));
592 	val |= MVEBU_COMPHY_RX_CTRL1_RXCLK2X_SEL |
594 	writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));
596 	val = readl(priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));
597 	val |= MVEBU_COMPHY_DTL_CTRL_DTL_FLOOP_EN;
598 	writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));
601 	val = readl(priv->base + MVEBU_COMPHY_SPEED_DIV(lane->id));
602 	val |= MVEBU_COMPHY_SPEED_DIV_TX_FORCE;
603 	writel(val, priv->base + MVEBU_COMPHY_SPEED_DIV(lane->id));
605 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id));
606 	val |= MVEBU_COMPHY_SERDES_CFG2_DFE_EN;
607 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id));
610 	val = readl(priv->base + MVEBU_COMPHY_DFE_RES(lane->id));
611 	val |= MVEBU_COMPHY_DFE_RES_FORCE_GEN_TBL;
612 	writel(val, priv->base + MVEBU_COMPHY_DFE_RES(lane->id));
614 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));
615 	val &= ~(MVEBU_COMPHY_GEN1_S0_TX_AMP(0x1f) |
617 	val |= MVEBU_COMPHY_GEN1_S0_TX_AMP(0x1c) |
619 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));
621 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S2(lane->id));
622 	val &= ~MVEBU_COMPHY_GEN1_S2_TX_EMPH(0xf);
623 	val |= MVEBU_COMPHY_GEN1_S2_TX_EMPH_EN;
624 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S2(lane->id));
626 	val = readl(priv->base + MVEBU_COMPHY_TX_SLEW_RATE(lane->id));
627 	val |= MVEBU_COMPHY_TX_SLEW_RATE_EMPH(0x3) |
629 	writel(val, priv->base + MVEBU_COMPHY_TX_SLEW_RATE(lane->id));
632 	val = readl(priv->base + MVEBU_COMPHY_IMP_CAL(lane->id));
633 	val &= ~MVEBU_COMPHY_IMP_CAL_TX_EXT(0x1f);
634 	val |= MVEBU_COMPHY_IMP_CAL_TX_EXT(0xe) |
636 	writel(val, priv->base + MVEBU_COMPHY_IMP_CAL(lane->id));
638 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S5(lane->id));
639 	val &= ~MVEBU_COMPHY_GEN1_S5_ICP(0xf);
640 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S5(lane->id));
642 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S1(lane->id));
643 	val &= ~(MVEBU_COMPHY_GEN1_S1_RX_MUL_PI(0x7) |
647 	val |= MVEBU_COMPHY_GEN1_S1_RX_DFE_EN |
652 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S1(lane->id));
654 	val = readl(priv->base + MVEBU_COMPHY_COEF(lane->id));
655 	val &= ~(MVEBU_COMPHY_COEF_DFE_EN | MVEBU_COMPHY_COEF_DFE_CTRL);
656 	writel(val, priv->base + MVEBU_COMPHY_COEF(lane->id));
658 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S4(lane->id));
659 	val &= ~MVEBU_COMPHY_GEN1_S4_DFE_RES(0x3);
660 	val |= MVEBU_COMPHY_GEN1_S4_DFE_RES(0x1);
661 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S4(lane->id));
663 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S3(lane->id));
664 	val |= MVEBU_COMPHY_GEN1_S3_FBCK_SEL;
665 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S3(lane->id));
668 	val = readl(priv->base + MVEBU_COMPHY_TRAINING5(lane->id));
669 	val &= ~MVEBU_COMPHY_TRAINING5_RX_TIMER(0x3ff);
670 	val |= MVEBU_COMPHY_TRAINING5_RX_TIMER(0x13);
671 	writel(val, priv->base + MVEBU_COMPHY_TRAINING5(lane->id));
674 	val = readl(priv->base + MVEBU_COMPHY_TRAINING0(lane->id));
675 	val |= MVEBU_COMPHY_TRAINING0_P2P_HOLD;
676 	writel(val, priv->base + MVEBU_COMPHY_TRAINING0(lane->id));
678 	val = readl(priv->base + MVEBU_COMPHY_TX_PRESET(lane->id));
679 	val &= ~MVEBU_COMPHY_TX_PRESET_INDEX(0xf);
680 	val |= MVEBU_COMPHY_TX_PRESET_INDEX(0x2);	/* preset coeff */
681 	writel(val, priv->base + MVEBU_COMPHY_TX_PRESET(lane->id));
683 	val = readl(priv->base + MVEBU_COMPHY_FRAME_DETECT3(lane->id));
684 	val &= ~MVEBU_COMPHY_FRAME_DETECT3_LOST_TIMEOUT_EN;
685 	writel(val, priv->base + MVEBU_COMPHY_FRAME_DETECT3(lane->id));
687 	val = readl(priv->base + MVEBU_COMPHY_TX_TRAIN_PRESET(lane->id));
688 	val |= MVEBU_COMPHY_TX_TRAIN_PRESET_16B_AUTO_EN |
690 	writel(val, priv->base + MVEBU_COMPHY_TX_TRAIN_PRESET(lane->id));
692 	val = readl(priv->base + MVEBU_COMPHY_FRAME_DETECT0(lane->id));
693 	val &= ~MVEBU_COMPHY_FRAME_DETECT0_PATN(0x1ff);
694 	val |= MVEBU_COMPHY_FRAME_DETECT0_PATN(0x88);
695 	writel(val, priv->base + MVEBU_COMPHY_FRAME_DETECT0(lane->id));
697 	val = readl(priv->base + MVEBU_COMPHY_DME(lane->id));
698 	val |= MVEBU_COMPHY_DME_ETH_MODE;
699 	writel(val, priv->base + MVEBU_COMPHY_DME(lane->id));
701 	val = readl(priv->base + MVEBU_COMPHY_VDD_CAL0(lane->id));
702 	val |= MVEBU_COMPHY_VDD_CAL0_CONT_MODE;
703 	writel(val, priv->base + MVEBU_COMPHY_VDD_CAL0(lane->id));
705 	val = readl(priv->base + MVEBU_SP_CALIB(lane->id));
706 	val &= ~MVEBU_SP_CALIB_SAMPLER(0x3);
707 	val |= MVEBU_SP_CALIB_SAMPLER(0x3) |
709 	writel(val, priv->base + MVEBU_SP_CALIB(lane->id));
710 	val &= ~MVEBU_SP_CALIB_SAMPLER_EN;
711 	writel(val, priv->base + MVEBU_SP_CALIB(lane->id));
714 	val = readl(priv->base + MVEBU_COMPHY_EXT_SELV(lane->id));
715 	val &= ~MVEBU_COMPHY_EXT_SELV_RX_SAMPL(0x1f);
716 	val |= MVEBU_COMPHY_EXT_SELV_RX_SAMPL(0x1a);
717 	writel(val, priv->base + MVEBU_COMPHY_EXT_SELV(lane->id));
727 	u32 val;
734 	regmap_read(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, &val);
735 	val &= ~(0xf << MVEBU_COMPHY_PIPE_SELECTOR_PIPE(lane->id));
736 	regmap_write(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, val);
738 	regmap_read(priv->regmap, MVEBU_COMPHY_SELECTOR, &val);
739 	val &= ~(0xf << MVEBU_COMPHY_SELECTOR_PHY(lane->id));
740 	val |= mux << MVEBU_COMPHY_SELECTOR_PHY(lane->id);
741 	regmap_write(priv->regmap, MVEBU_COMPHY_SELECTOR, val);
759 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
760 	val |= MVEBU_COMPHY_SERDES_CFG1_RF_RESET;
761 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
878 	u32 val;
880 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
881 	val &= ~(MVEBU_COMPHY_SERDES_CFG1_RESET |
884 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
886 	regmap_read(priv->regmap, MVEBU_COMPHY_SELECTOR, &val);
887 	val &= ~(0xf << MVEBU_COMPHY_SELECTOR_PHY(lane->id));
888 	regmap_write(priv->regmap, MVEBU_COMPHY_SELECTOR, val);
890 	regmap_read(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, &val);
891 	val &= ~(0xf << MVEBU_COMPHY_PIPE_SELECTOR_PIPE(lane->id));
892 	regmap_write(priv->regmap, MVEBU_COMPHY_PIPE_SELECTOR, val);
1039 		u32 val;
1041 		ret = of_property_read_u32(child, "reg", &val);
1048 		if (val >= MVEBU_COMPHY_LANES) {
1070 		lane->id = val;