phy/marvell/phy-mvebu-cp110-comphy.c

129  * A lane is described by the following bitfields:
182 	unsigned lane;
190 		.lane = _lane,				\
200 		.lane = _lane,				\
209 	/* lane 0 */
214 	/* lane 1 */
221 	/* lane 2 */
230 	/* lane 3 */
237 	/* lane 4 */
250 	/* lane 5 */
277 			    unsigned long lane, unsigned long mode)
282 	arm_smccc_smc(function, phys, lane, mode, 0, 0, 0, 0, &res);
295 static int mvebu_comphy_get_mode(bool fw_mode, int lane, int port,
309 		if (conf->lane == lane &&
325 static inline int mvebu_comphy_get_mux(int lane, int port,
328 	return mvebu_comphy_get_mode(false, lane, port, mode, submode);
331 static inline int mvebu_comphy_get_fw_mode(int lane, int port,
334 	return mvebu_comphy_get_mode(true, lane, port, mode, submode);
337 static int mvebu_comphy_ethernet_init_reset(struct mvebu_comphy_lane *lane)
339 	struct mvebu_comphy_priv *priv = lane->priv;
342 	regmap_read(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), &val);
345 	regmap_write(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), val);
348 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id));
357 	switch (lane->submode) {
379 			"unsupported comphy submode (%d) on lane %d\n",
380 			lane->submode,
381 			lane->id);
385 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id));
387 	if (lane->submode == PHY_INTERFACE_MODE_RXAUI) {
390 		switch (lane->id) {
401 				"RXAUI is not supported on comphy lane %d\n",
402 				lane->id);
410 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
414 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
417 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
420 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
426 	regmap_read(priv->regmap, MVEBU_COMPHY_CONF6(lane->id), &val);
428 	regmap_write(priv->regmap, MVEBU_COMPHY_CONF6(lane->id), val);
431 	val = readl(priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id));
433 	if (lane->submode == PHY_INTERFACE_MODE_10GBASER)
435 	writel(val, priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id));
438 	val = readl(priv->base + MVEBU_COMPHY_PWRPLL_CTRL(lane->id));
443 	writel(val, priv->base + MVEBU_COMPHY_PWRPLL_CTRL(lane->id));
445 	val = readl(priv->base + MVEBU_COMPHY_LOOPBACK(lane->id));
448 	writel(val, priv->base + MVEBU_COMPHY_LOOPBACK(lane->id));
453 static int mvebu_comphy_init_plls(struct mvebu_comphy_lane *lane)
455 	struct mvebu_comphy_priv *priv = lane->priv;
459 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id));
463 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id));
466 	readl_poll_timeout(priv->base + MVEBU_COMPHY_SERDES_STATUS0(lane->id),
476 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
478 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
481 	readl_poll_timeout(priv->base + MVEBU_COMPHY_SERDES_STATUS0(lane->id),
487 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
489 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
496 	struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
497 	struct mvebu_comphy_priv *priv = lane->priv;
501 	err = mvebu_comphy_ethernet_init_reset(lane);
505 	val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));
508 	writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));
510 	val = readl(priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));
512 	writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));
514 	regmap_read(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), &val);
517 	regmap_write(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), val);
519 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));
522 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));
524 	return mvebu_comphy_init_plls(lane);
529 	struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
530 	struct mvebu_comphy_priv *priv = lane->priv;
534 	err = mvebu_comphy_ethernet_init_reset(lane);
538 	val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));
541 	writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));
543 	val = readl(priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));
545 	writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));
547 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id));
549 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id));
551 	val = readl(priv->base + MVEBU_COMPHY_DFE_RES(lane->id));
553 	writel(val, priv->base + MVEBU_COMPHY_DFE_RES(lane->id));
555 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));
558 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));
560 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S1(lane->id));
566 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S1(lane->id));
568 	val = readl(priv->base + MVEBU_COMPHY_COEF(lane->id));
570 	writel(val, priv->base + MVEBU_COMPHY_COEF(lane->id));
572 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S4(lane->id));
575 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S4(lane->id));
577 	return mvebu_comphy_init_plls(lane);
582 	struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
583 	struct mvebu_comphy_priv *priv = lane->priv;
587 	err = mvebu_comphy_ethernet_init_reset(lane);
591 	val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));
594 	writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));
596 	val = readl(priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));
598 	writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));
601 	val = readl(priv->base + MVEBU_COMPHY_SPEED_DIV(lane->id));
603 	writel(val, priv->base + MVEBU_COMPHY_SPEED_DIV(lane->id));
605 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id));
607 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id));
610 	val = readl(priv->base + MVEBU_COMPHY_DFE_RES(lane->id));
612 	writel(val, priv->base + MVEBU_COMPHY_DFE_RES(lane->id));
614 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));
619 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));
621 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S2(lane->id));
624 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S2(lane->id));
626 	val = readl(priv->base + MVEBU_COMPHY_TX_SLEW_RATE(lane->id));
629 	writel(val, priv->base + MVEBU_COMPHY_TX_SLEW_RATE(lane->id));
632 	val = readl(priv->base + MVEBU_COMPHY_IMP_CAL(lane->id));
636 	writel(val, priv->base + MVEBU_COMPHY_IMP_CAL(lane->id));
638 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S5(lane->id));
640 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S5(lane->id));
642 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S1(lane->id));
652 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S1(lane->id));
654 	val = readl(priv->base + MVEBU_COMPHY_COEF(lane->id));
656 	writel(val, priv->base + MVEBU_COMPHY_COEF(lane->id));
658 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S4(lane->id));
661 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S4(lane->id));
663 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S3(lane->id));
665 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S3(lane->id));
668 	val = readl(priv->base + MVEBU_COMPHY_TRAINING5(lane->id));
671 	writel(val, priv->base + MVEBU_COMPHY_TRAINING5(lane->id));
674 	val = readl(priv->base + MVEBU_COMPHY_TRAINING0(lane->id));
676 	writel(val, priv->base + MVEBU_COMPHY_TRAINING0(lane->id));
678 	val = readl(priv->base + MVEBU_COMPHY_TX_PRESET(lane->id));
681 	writel(val, priv->base + MVEBU_COMPHY_TX_PRESET(lane->id));
683 	val = readl(priv->base + MVEBU_COMPHY_FRAME_DETECT3(lane->id));
685 	writel(val, priv->base + MVEBU_COMPHY_FRAME_DETECT3(lane->id));
687 	val = readl(priv->base + MVEBU_COMPHY_TX_TRAIN_PRESET(lane->id));
690 	writel(val, priv->base + MVEBU_COMPHY_TX_TRAIN_PRESET(lane->id));
692 	val = readl(priv->base + MVEBU_COMPHY_FRAME_DETECT0(lane->id));
695 	writel(val, priv->base + MVEBU_COMPHY_FRAME_DETECT0(lane->id));
697 	val = readl(priv->base + MVEBU_COMPHY_DME(lane->id));
699 	writel(val, priv->base + MVEBU_COMPHY_DME(lane->id));
701 	val = readl(priv->base + MVEBU_COMPHY_VDD_CAL0(lane->id));
703 	writel(val, priv->base + MVEBU_COMPHY_VDD_CAL0(lane->id));
705 	val = readl(priv->base + MVEBU_SP_CALIB(lane->id));
709 	writel(val, priv->base + MVEBU_SP_CALIB(lane->id));
711 	writel(val, priv->base + MVEBU_SP_CALIB(lane->id));
714 	val = readl(priv->base + MVEBU_COMPHY_EXT_SELV(lane->id));
717 	writel(val, priv->base + MVEBU_COMPHY_EXT_SELV(lane->id));
719 	return mvebu_comphy_init_plls(lane);
724 	struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
725 	struct mvebu_comphy_priv *priv = lane->priv;
729 	mux = mvebu_comphy_get_mux(lane->id, lane->port,
730 				   lane->mode, lane->submode);
735 	val &= ~(0xf << MVEBU_COMPHY_PIPE_SELECTOR_PIPE(lane->id));
739 	val &= ~(0xf << MVEBU_COMPHY_SELECTOR_PHY(lane->id));
740 	val |= mux << MVEBU_COMPHY_SELECTOR_PHY(lane->id);
743 	switch (lane->submode) {
759 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
761 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
768 	struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
769 	struct mvebu_comphy_priv *priv = lane->priv;
774 	fw_mode = mvebu_comphy_get_fw_mode(lane->id, lane->port,
775 					   lane->mode, lane->submode);
780 	switch (lane->mode) {
782 		switch (lane->submode) {
784 			dev_dbg(priv->dev, "set lane %d to RXAUI mode\n",
785 				lane->id);
789 			dev_dbg(priv->dev, "set lane %d to 1000BASE-X mode\n",
790 				lane->id);
794 			dev_dbg(priv->dev, "set lane %d to 2500BASE-X mode\n",
795 				lane->id);
799 			dev_dbg(priv->dev, "set lane %d to 5GBASE-R mode\n",
800 				lane->id);
804 			dev_dbg(priv->dev, "set lane %d to 10GBASE-R mode\n",
805 				lane->id);
810 				lane->submode);
813 		fw_param = COMPHY_FW_PARAM_ETH(fw_mode, lane->port, fw_speed);
817 		dev_dbg(priv->dev, "set lane %d to USB3 mode\n", lane->id);
818 		fw_param = COMPHY_FW_PARAM(fw_mode, lane->port);
821 		dev_dbg(priv->dev, "set lane %d to SATA mode\n", lane->id);
822 		fw_param = COMPHY_FW_PARAM(fw_mode, lane->port);
825 		dev_dbg(priv->dev, "set lane %d to PCIe mode (x%d)\n", lane->id,
826 			lane->submode);
827 		fw_param = COMPHY_FW_PARAM_PCIE(fw_mode, lane->port,
828 						lane->submode);
831 		dev_err(priv->dev, "unsupported PHY mode (%d)\n", lane->mode);
835 	ret = mvebu_comphy_smc(COMPHY_SIP_POWER_ON, priv->cp_phys, lane->id,
846 		 lane->id, lane->mode, ret);
856 	struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
861 	if (mvebu_comphy_get_fw_mode(lane->id, lane->port, mode, submode) < 0)
864 	lane->mode = mode;
865 	lane->submode = submode;
868 	if (mode == PHY_MODE_PCIE && !lane->submode)
869 		lane->submode = 1;
876 	struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
877 	struct mvebu_comphy_priv *priv = lane->priv;
880 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
884 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
887 	val &= ~(0xf << MVEBU_COMPHY_SELECTOR_PHY(lane->id));
891 	val &= ~(0xf << MVEBU_COMPHY_PIPE_SELECTOR_PIPE(lane->id));
899 	struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
900 	struct mvebu_comphy_priv *priv = lane->priv;
904 			       lane->id, 0);
922 	struct mvebu_comphy_lane *lane;
932 	lane = phy_get_drvdata(phy);
933 	lane->port = args->args[0];
1037 		struct mvebu_comphy_lane *lane;
1053 		lane = devm_kzalloc(&pdev->dev, sizeof(*lane), GFP_KERNEL);
1054 		if (!lane) {
1067 		lane->priv = priv;
1068 		lane->mode = PHY_MODE_INVALID;
1069 		lane->submode = PHY_INTERFACE_MODE_NA;
1070 		lane->id = val;
1071 		lane->port = -1;
1072 		phy_set_drvdata(phy, lane);