phy/marvell/phy-armada38x-comphy.c

47 	struct a38x_comphy_lane lane[MAX_A38X_COMPHY];
52  * row index = serdes lane,
64 static void a38x_set_conf(struct a38x_comphy_lane *lane, bool enable)
66 	struct a38x_comphy *priv = lane->priv;
72 			conf |= BIT(lane->port);
74 			conf &= ~BIT(lane->port);
79 static void a38x_comphy_set_reg(struct a38x_comphy_lane *lane,
84 	val = readl_relaxed(lane->base + offset) & ~mask;
85 	writel(val | value, lane->base + offset);
88 static void a38x_comphy_set_speed(struct a38x_comphy_lane *lane,
91 	a38x_comphy_set_reg(lane, COMPHY_CFG1,
97 static int a38x_comphy_poll(struct a38x_comphy_lane *lane,
103 	ret = readl_relaxed_poll_timeout_atomic(lane->base + offset, val,
108 		dev_err(lane->priv->dev,
109 			"comphy%u: timed out waiting for status\n", lane->n);
120 	struct a38x_comphy_lane *lane = phy_get_drvdata(phy);
141 	a38x_set_conf(lane, false);
143 	a38x_comphy_set_speed(lane, gen, gen);
145 	ret = a38x_comphy_poll(lane, COMPHY_STAT1,
152 		a38x_set_conf(lane, true);
165 	struct a38x_comphy_lane *lane;
176 	lane = phy_get_drvdata(phy);
177 	if (lane->port >= 0)
180 	lane->port = args->args[0];
182 	val = readl_relaxed(lane->priv->base + COMPHY_SELECTOR);
183 	val = (val >> (4 * lane->n)) & 0xf;
185 	if (!gbe_mux[lane->n][lane->port] ||
186 	    val != gbe_mux[lane->n][lane->port]) {
187 		dev_warn(lane->priv->dev,
188 			 "comphy%u: not configured for GBE\n", lane->n);
234 		if (val >= MAX_A38X_COMPHY || priv->lane[val].base) {
245 		priv->lane[val].base = base + 0x28 * val;
246 		priv->lane[val].priv = priv;
247 		priv->lane[val].n = val;
248 		priv->lane[val].port = -1;
249 		phy_set_drvdata(phy, &priv->lane[val]);