phy/intel/phy-intel-lgm-emmc.c

47 	struct regmap *syscfg;
64 	ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL1_REG, PDB_MASK,
88 	ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL1_REG, PDB_MASK,
102 	ret = regmap_read_poll_timeout(priv->syscfg, EMMC_PHYSTAT_REG,
111 	ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL2_REG, FRQSEL_MASK,
119 	ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL1_REG, ENDLL_MASK,
140 	ret = regmap_read_poll_timeout(priv->syscfg,
193 	ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL0_REG, DR_TY_MASK,
201 	ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL0_REG, OTAPDLYENA,
209 	ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL0_REG,
247 	priv->syscfg = syscon_regmap_lookup_by_phandle(np, "intel,syscon");
248 	if (IS_ERR(priv->syscfg)) {
250 		return PTR_ERR(priv->syscfg);