phy/intel/phy-intel-keembay-emmc.c

60 	int ret;
66 	ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, PWR_DOWN_MASK,
68 	if (ret) {
69 		dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret);
70 		return ret;
73 	ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, DLL_EN_MASK,
75 	if (ret) {
76 		dev_err(&phy->dev, "turn off the dll failed: %d\n", ret);
77 		return ret;
109 	ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, PWR_DOWN_MASK,
111 	if (ret) {
112 		dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret);
113 		return ret;
123 	ret = regmap_read_poll_timeout(priv->syscfg, PHY_STAT,
126 	if (ret) {
127 		dev_err(&phy->dev, "caldone failed, ret=%d\n", ret);
128 		return ret;
132 	ret = regmap_update_bits(priv->syscfg, PHY_CFG_2, SEL_FREQ_MASK,
134 	if (ret) {
135 		dev_err(&phy->dev, "set the frequency of dll failed:%d\n", ret);
136 		return ret;
140 	ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, DLL_EN_MASK,
142 	if (ret) {
143 		dev_err(&phy->dev, "turn on the dll failed: %d\n", ret);
144 		return ret;
173 	ret = regmap_read_poll_timeout(priv->syscfg, PHY_STAT,
176 	if (ret)
177 		dev_err(&phy->dev, "dllrdy failed, ret=%d\n", ret);
179 	return ret;
215 	int ret;
218 	ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, SEL_DLY_TXCLK_MASK,
220 	if (ret) {
221 		dev_err(&phy->dev, "ERROR: delay chain txclk set: %d\n", ret);
222 		return ret;
226 	ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, OTAP_DLY_ENA_MASK,
228 	if (ret) {
229 		dev_err(&phy->dev, "ERROR: output tap delay set: %d\n", ret);
230 		return ret;
234 	ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, OTAP_DLY_SEL_MASK,
236 	if (ret) {
237 		dev_err(&phy->dev, "ERROR: output tap delay select: %d\n", ret);
238 		return ret;