phy/hisilicon/phy-hi3670-pcie.c

168 static inline void hi3670_apb_phy_writel(struct hi3670_pcie_phy *phy, u32 val,
171 	writel(val, phy->base + APB_PHY_START_ADDR + reg);
180 					  u32 val, u32 mask, u32 reg)
186 	regval |= val;
191 						u32 val, u32 reg)
193 	writel(val, phy->base + reg);
204 	u32 val;
206 	regmap_read(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, &val);
207 	val |= PCIE_DEBOUNCE_PARAM;
209 		val &= ~PCIE_OE_BYPASS;
211 		val |= PCIE_OE_BYPASS;
212 	regmap_write(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, val);
235 	u32 val;
237 	val = kirin_apb_natural_phy_readl(phy, RAWLANEN_DIG_PCS_XF_TX_OVRD_IN_1);
240 		val &= ~EYE_PARM1_MASK;
241 		val |= FIELD_PREP(EYE_PARM1_MASK, phy->eye_param[1]);
242 		val |= EYE_PARM1_EN;
244 	kirin_apb_natural_phy_writel(phy, val,
247 	val = kirin_apb_natural_phy_readl(phy, LANEN_DIG_ASIC_TX_OVRD_IN_2);
248 	val &= ~(EYE_PARM2_MASK | EYE_PARM3_MASK);
250 		val |= FIELD_PREP(EYE_PARM2_MASK, phy->eye_param[2]);
251 		val |= EYE_PARM2_EN;
255 		val |= FIELD_PREP(EYE_PARM3_MASK, phy->eye_param[3]);
256 		val |= EYE_PARM3_EN;
259 	kirin_apb_natural_phy_writel(phy, val, LANEN_DIG_ASIC_TX_OVRD_IN_2);
261 	val = kirin_apb_natural_phy_readl(phy, SUP_DIG_LVL_OVRD_IN);
263 		val &= ~EYE_PARM0_MASK;
264 		val |= FIELD_PREP(EYE_PARM0_MASK, phy->eye_param[0]);
265 		val |= EYE_PARM0_EN;
267 	kirin_apb_natural_phy_writel(phy, val, SUP_DIG_LVL_OVRD_IN);
269 	val = kirin_apb_natural_phy_readl(phy, LANEN_DIG_ASIC_TX_OVRD_IN_1);
271 		val &= ~EYE_PARM4_MASK;
272 		val |= FIELD_PREP(EYE_PARM4_MASK, phy->eye_param[4]);
273 		val |= EYE_PARM4_EN;
275 	kirin_apb_natural_phy_writel(phy, val, LANEN_DIG_ASIC_TX_OVRD_IN_1);
280 	u32 val;
286 	regmap_read(phy->apb, SOC_PCIECTRL_CTRL7_ADDR, &val);
287 	val |= PCIE_PULL_UP_SYS_AUX_PWR_DET;
288 	regmap_write(phy->apb, SOC_PCIECTRL_CTRL7_ADDR, val);
291 	regmap_read(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, &val);
292 	val &= ~PCIE_OUTPUT_PULL_BITS;
293 	val |= PCIE_OUTPUT_PULL_DOWN;
294 	regmap_write(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, val);
337 	u32 val;
346 		val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_MMC1PLL_STAT0);
347 		while (!(val & FNPLL_HAS_LOCKED)) {
354 			val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_MMC1PLL_STAT0);
388 	unsigned int val;
390 	regmap_read(phy->crgctrl, CRGPERIPH_PCIECTRL0, &val);
393 		val &= ~IO_OE_HARD_GT_MODE; /* enable hard gt mode */
395 		val |= IO_OE_HARD_GT_MODE; /* disable hard gt mode */
397 	regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val);
405 	unsigned int val;
407 	regmap_read(phy->crgctrl, CRGPERIPH_PCIECTRL0, &val);
410 	val |= IO_IE_EN_HARD_BYPASS;
413 	val &= ~IO_HARD_CTRL_DEBOUNCE_BYPASS;
416 	val |= (DEBOUNCE_WAITCFG_IN | DEBOUNCE_WAITCFG_OUT);
419 	val |= IO_OE_GT_MODE;
422 		val &= ~IO_OE_EN_HARD_BYPASS;
424 		val |= IO_OE_EN_HARD_BYPASS;
426 	regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val);
431 	unsigned int val;
440 		regmap_read(phy->crgctrl, CRGPERIPH_PCIECTRL0, &val);
441 		val &= ~IO_REF_HARD_GT_MODE;
442 		regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val);
450 		regmap_read(phy->crgctrl, CRGPERIPH_PCIECTRL0, &val);
451 		val |= IO_REF_HARD_GT_MODE;
452 		regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val);
506 	u32 val;
510 	val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_STATE0_ADDR);
511 	while (val & pipe_clk_stable) {
518 		val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_STATE0_ADDR);
528 	unsigned int val = NOC_PW_MASK;
532 		val = NOC_PW_MASK | NOC_PW_SET_BIT;
534 		val = NOC_PW_MASK;
537 	regmap_write(phy->pmctrl, NOC_POWER_IDLEREQ_1, val);
540 	regmap_read(phy->pmctrl, NOC_POWER_IDLE_1, &val);
541 	while ((val & NOC_PW_SET_BIT) != rst) {
548 		regmap_read(phy->pmctrl, NOC_POWER_IDLE_1, &val);
663 	int val, ret;
693 	regmap_read(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, &val);
694 	val |= PCIE_DEASSERT_CONTROLLER_PERST;
695 	regmap_write(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, val);