phy/amlogic/phy-meson-axg-mipi-dphy.c

185 	struct phy_meson_axg_mipi_dphy_priv *priv = phy_get_drvdata(phy);
188 	ret = phy_init(priv->analog);
192 	ret = reset_control_reset(priv->reset);
202 	struct phy_meson_axg_mipi_dphy_priv *priv = phy_get_drvdata(phy);
209 	ret = phy_configure(priv->analog, opts);
213 	memcpy(&priv->config, opts, sizeof(priv->config));
220 	struct phy_meson_axg_mipi_dphy_priv *priv = phy_get_drvdata(phy);
224 	ret = phy_power_on(priv->analog);
229 	regmap_write(priv->regmap, MIPI_DSI_PHY_CTRL,  0x1);
230 	regmap_write(priv->regmap, MIPI_DSI_PHY_CTRL,
236 	regmap_update_bits(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(9), BIT(9));
239 	regmap_update_bits(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(12), BIT(12));
240 	regmap_update_bits(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(31), BIT(31));
241 	regmap_update_bits(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(31), 0);
244 	temp = (1000000 * 100) / (priv->config.hs_clk_rate / 1000);
247 	regmap_write(priv->regmap, MIPI_DSI_CLK_TIM,
248 		     DIV_ROUND_UP(priv->config.clk_trail, temp) |
249 		     (DIV_ROUND_UP(priv->config.clk_post +
250 				   priv->config.hs_trail, temp) << 8) |
251 		     (DIV_ROUND_UP(priv->config.clk_zero, temp) << 16) |
252 		     (DIV_ROUND_UP(priv->config.clk_prepare, temp) << 24));
253 	regmap_write(priv->regmap, MIPI_DSI_CLK_TIM1,
254 		     DIV_ROUND_UP(priv->config.clk_pre, BITS_PER_BYTE));
256 	regmap_write(priv->regmap, MIPI_DSI_HS_TIM,
257 		     DIV_ROUND_UP(priv->config.hs_exit, temp) |
258 		     (DIV_ROUND_UP(priv->config.hs_trail, temp) << 8) |
259 		     (DIV_ROUND_UP(priv->config.hs_zero, temp) << 16) |
260 		     (DIV_ROUND_UP(priv->config.hs_prepare, temp) << 24));
262 	regmap_write(priv->regmap, MIPI_DSI_LP_TIM,
263 		     DIV_ROUND_UP(priv->config.lpx, temp) |
264 		     (DIV_ROUND_UP(priv->config.ta_sure, temp) << 8) |
265 		     (DIV_ROUND_UP(priv->config.ta_go, temp) << 16) |
266 		     (DIV_ROUND_UP(priv->config.ta_get, temp) << 24));
268 	regmap_write(priv->regmap, MIPI_DSI_ANA_UP_TIM, 0x0100);
269 	regmap_write(priv->regmap, MIPI_DSI_INIT_TIM,
270 		     DIV_ROUND_UP(priv->config.init * NSEC_PER_MSEC, temp));
271 	regmap_write(priv->regmap, MIPI_DSI_WAKEUP_TIM,
272 		     DIV_ROUND_UP(priv->config.wakeup * NSEC_PER_MSEC, temp));
273 	regmap_write(priv->regmap, MIPI_DSI_LPOK_TIM, 0x7C);
274 	regmap_write(priv->regmap, MIPI_DSI_ULPS_CHECK, 0x927C);
275 	regmap_write(priv->regmap, MIPI_DSI_LP_WCHDOG, 0x1000);
276 	regmap_write(priv->regmap, MIPI_DSI_TURN_WCHDOG, 0x1000);
279 	switch (priv->config.lanes) {
281 		regmap_write(priv->regmap, MIPI_DSI_CHAN_CTRL, 0xe);
284 		regmap_write(priv->regmap, MIPI_DSI_CHAN_CTRL, 0xc);
287 		regmap_write(priv->regmap, MIPI_DSI_CHAN_CTRL, 0x8);
291 		regmap_write(priv->regmap, MIPI_DSI_CHAN_CTRL, 0);
296 	regmap_update_bits(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(1), BIT(1));
303 	struct phy_meson_axg_mipi_dphy_priv *priv = phy_get_drvdata(phy);
305 	regmap_write(priv->regmap, MIPI_DSI_CHAN_CTRL, 0xf);
306 	regmap_write(priv->regmap, MIPI_DSI_PHY_CTRL, BIT(31));
308 	phy_power_off(priv->analog);
315 	struct phy_meson_axg_mipi_dphy_priv *priv = phy_get_drvdata(phy);
318 	ret = phy_exit(priv->analog);
322 	return reset_control_reset(priv->reset);
338 	struct phy_meson_axg_mipi_dphy_priv *priv;
343 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
344 	if (!priv)
347 	priv->dev = dev;
348 	platform_set_drvdata(pdev, priv);
354 	priv->regmap = devm_regmap_init_mmio(dev, base,
356 	if (IS_ERR(priv->regmap))
357 		return PTR_ERR(priv->regmap);
359 	priv->clk = devm_clk_get(dev, "pclk");
360 	if (IS_ERR(priv->clk))
361 		return PTR_ERR(priv->clk);
363 	priv->reset = devm_reset_control_get(dev, "phy");
364 	if (IS_ERR(priv->reset))
365 		return PTR_ERR(priv->reset);
367 	priv->analog = devm_phy_get(dev, "analog");
368 	if (IS_ERR(priv->analog))
369 		return PTR_ERR(priv->analog);
371 	ret = clk_prepare_enable(priv->clk);
375 	ret = reset_control_deassert(priv->reset);
388 	phy_set_drvdata(phy, priv);