drivers/perf/xgene_pmu.c

91 	struct hw_pmu_info *inf;
140 	struct hw_pmu_info inf;
732 	return readl(pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx));
757 	writel(val, pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx));
776 	writel(val, pmu_dev->inf->csr + PMU_PMEVTYPER0 + (4 * idx));
782 	writel(val, pmu_dev->inf->csr + PMU_PMAMR0);
791 	writel(val, pmu_dev->inf->csr + PMU_PMAMR1);
802 	val = readl(pmu_dev->inf->csr + PMU_PMCNTENSET);
804 	writel(val, pmu_dev->inf->csr + PMU_PMCNTENSET);
812 	val = readl(pmu_dev->inf->csr + PMU_PMCNTENCLR);
814 	writel(val, pmu_dev->inf->csr + PMU_PMCNTENCLR);
822 	val = readl(pmu_dev->inf->csr + PMU_PMINTENSET);
824 	writel(val, pmu_dev->inf->csr + PMU_PMINTENSET);
832 	val = readl(pmu_dev->inf->csr + PMU_PMINTENCLR);
834 	writel(val, pmu_dev->inf->csr + PMU_PMINTENCLR);
841 	val = readl(pmu_dev->inf->csr + PMU_PMCR);
843 	writel(val, pmu_dev->inf->csr + PMU_PMCR);
850 	val = readl(pmu_dev->inf->csr + PMU_PMCR);
852 	writel(val, pmu_dev->inf->csr + PMU_PMCR);
859 	val = readl(pmu_dev->inf->csr + PMU_PMCR);
861 	writel(val, pmu_dev->inf->csr + PMU_PMCR);
950 	if (pmu_dev->inf->type == PMU_TYPE_IOB)
1136 	pmu->inf = &ctx->inf;
1139 	switch (pmu->inf->type) {
1141 		if (!(xgene_pmu->l3c_active_mask & pmu->inf->enable_mask))
1159 		if (!(xgene_pmu->mcb_active_mask & pmu->inf->enable_mask))
1167 		if (!(xgene_pmu->mc_active_mask & pmu->inf->enable_mask))
1191 	void __iomem *csr = pmu_dev->inf->csr;
1459 	struct hw_pmu_info *inf;
1510 	inf = &ctx->inf;
1511 	inf->type = type;
1512 	inf->csr = dev_csr;
1513 	inf->enable_mask = 1 << enable_bit;
1573 	switch (ctx->inf.type) {
1627 	struct hw_pmu_info *inf;
1657 	inf = &ctx->inf;
1658 	inf->type = type;
1659 	inf->csr = dev_csr;
1660 	inf->enable_mask = 1 << enable_bit;
1695 		switch (ctx->inf.type) {