drivers/perf/riscv_pmu_sbi.c

11 #define pr_fmt(fmt) "riscv-pmu-sbi: " fmt
86  * per_cpu in case of harts with different pmu counters
372 	struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);
431 	struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu);
514 static void pmu_sbi_snapshot_free(struct riscv_pmu *pmu)
519 		struct cpu_hw_events *cpu_hw_evt = per_cpu_ptr(pmu->hw_events, cpu);
530 static int pmu_sbi_snapshot_alloc(struct riscv_pmu *pmu)
536 		struct cpu_hw_events *cpu_hw_evt = per_cpu_ptr(pmu->hw_events, cpu);
540 			pmu_sbi_snapshot_free(pmu);
564 static int pmu_sbi_snapshot_setup(struct riscv_pmu *pmu, int cpu)
569 	cpu_hw_evt = per_cpu_ptr(pmu->hw_events, cpu);
587 			pr_warn("pmu snapshot setup failed with error %ld\n", ret.error);
603 	struct riscv_pmu *pmu = to_riscv_pmu(event->pmu);
604 	struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events);
684 	struct riscv_pmu *pmu = to_riscv_pmu(event->pmu);
685 	struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events);
758 static inline void pmu_sbi_stop_all(struct riscv_pmu *pmu)
765 		  0, pmu->cmask, 0, 0, 0, 0);
768 static inline void pmu_sbi_stop_hw_ctrs(struct riscv_pmu *pmu)
770 	struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events);
886 static void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu,
889 	struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events);
904 	struct riscv_pmu *pmu;
928 	pmu = to_riscv_pmu(event->pmu);
929 	pmu_sbi_stop_hw_ctrs(pmu);
998 	pmu_sbi_start_overflow_mask(pmu, overflowed_ctrs);
1006 	struct riscv_pmu *pmu = hlist_entry_safe(node, struct riscv_pmu, node);
1007 	struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events);
1019 	pmu_sbi_stop_all(pmu);
1028 		return pmu_sbi_snapshot_setup(pmu, cpu);
1048 static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, struct platform_device *pdev)
1051 	struct cpu_hw_events __percpu *hw_events = pmu->hw_events;
1087 	ret = request_percpu_irq(riscv_pmu_irq, pmu_sbi_ovf_handler, "riscv-pmu", hw_events);
1136 static int riscv_pm_pmu_register(struct riscv_pmu *pmu)
1138 	pmu->riscv_pm_nb.notifier_call = riscv_pm_pmu_notify;
1139 	return cpu_pm_register_notifier(&pmu->riscv_pm_nb);
1142 static void riscv_pm_pmu_unregister(struct riscv_pmu *pmu)
1144 	cpu_pm_unregister_notifier(&pmu->riscv_pm_nb);
1147 static inline int riscv_pm_pmu_register(struct riscv_pmu *pmu) { return 0; }
1148 static inline void riscv_pm_pmu_unregister(struct riscv_pmu *pmu) { }
1151 static void riscv_pmu_destroy(struct riscv_pmu *pmu)
1156 			pmu_sbi_snapshot_free(pmu);
1159 	riscv_pm_pmu_unregister(pmu);
1160 	cpuhp_state_remove_instance(CPUHP_AP_PERF_RISCV_STARTING, &pmu->node);
1279 	struct riscv_pmu *pmu = NULL;
1284 	pmu = riscv_pmu_alloc();
1285 	if (!pmu)
1304 	ret = pmu_sbi_setup_irqs(pmu, pdev);
1307 		pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
1308 		pmu->pmu.capabilities |= PERF_PMU_CAP_NO_EXCLUDE;
1311 	pmu->pmu.attr_groups = riscv_pmu_attr_groups;
1312 	pmu->pmu.parent = &pdev->dev;
1313 	pmu->cmask = cmask;
1314 	pmu->ctr_start = pmu_sbi_ctr_start;
1315 	pmu->ctr_stop = pmu_sbi_ctr_stop;
1316 	pmu->event_map = pmu_sbi_event_map;
1317 	pmu->ctr_get_idx = pmu_sbi_ctr_get_idx;
1318 	pmu->ctr_get_width = pmu_sbi_ctr_get_width;
1319 	pmu->ctr_clear_idx = pmu_sbi_ctr_clear_idx;
1320 	pmu->ctr_read = pmu_sbi_ctr_read;
1321 	pmu->event_init = pmu_sbi_event_init;
1322 	pmu->event_mapped = pmu_sbi_event_mapped;
1323 	pmu->event_unmapped = pmu_sbi_event_unmapped;
1324 	pmu->csr_index = pmu_sbi_csr_index;
1326 	ret = riscv_pm_pmu_register(pmu);
1330 	ret = perf_pmu_register(&pmu->pmu, "cpu", PERF_TYPE_RAW);
1336 		ret = pmu_sbi_snapshot_alloc(pmu);
1340 		ret = pmu_sbi_snapshot_setup(pmu, smp_processor_id());
1343 			pmu_sbi_snapshot_free(pmu);
1358 	ret = cpuhp_state_add_instance(CPUHP_AP_PERF_RISCV_STARTING, &pmu->node);
1365 	riscv_pmu_destroy(pmu);
1368 	kfree(pmu);
1393 				      "perf/riscv/pmu:starting",
1411 	/* Notify legacy implementation that SBI pmu is available*/