drivers/perf/marvell_cn10k_ddr_pmu.c

36 /* 8 Generic event counter + 2 fixed event counters */
44 /* Generic event counter registers */
104 /* Event counter value registers */
108 /* Fixed event counter enable/disable register */
113 /* Fixed event counter control register */
118 /* Fixed event counter value register */
258  * 48 bit counter incremented max at 5.6 GT/s, which may take many
295 	/* DDR read free-run counter index */
301 	/* DDR write free-run counter index */
318 static void cn10k_ddr_perf_free_counter(struct cn10k_ddr_pmu *pmu, int counter)
320 	pmu->events[counter] = NULL;
355 					  int counter, bool enable)
360 	if (counter > DDRC_PERF_NUM_COUNTERS) {
361 		pr_err("Error: unsupported counter %d\n", counter);
365 	if (counter < DDRC_PERF_NUM_GEN_COUNTERS) {
366 		reg = DDRC_PERF_CFG(counter);
378 			if (counter == DDRC_PERF_READ_COUNTER_IDX)
383 			if (counter == DDRC_PERF_READ_COUNTER_IDX)
392 static u64 cn10k_ddr_perf_read_counter(struct cn10k_ddr_pmu *pmu, int counter)
396 	if (counter == DDRC_PERF_READ_COUNTER_IDX)
399 	if (counter == DDRC_PERF_WRITE_COUNTER_IDX)
402 	val = readq_relaxed(pmu->base + DDRC_PERF_CNT_VALUE(counter));
426 	int counter = hwc->idx;
430 	cn10k_ddr_perf_counter_enable(pmu, counter, true);
440 	int counter, ret;
444 	counter = cn10k_ddr_perf_alloc_counter(pmu, event);
445 	if (counter < 0)
449 	hwc->idx = counter;
455 	if (counter < DDRC_PERF_NUM_GEN_COUNTERS) {
457 		reg_offset = DDRC_PERF_CFG(counter);
464 		/* fixed event counter, clear counter value */
465 		if (counter == DDRC_PERF_READ_COUNTER_IDX)
485 	int counter = hwc->idx;
487 	cn10k_ddr_perf_counter_enable(pmu, counter, false);
499 	int counter = hwc->idx;
503 	cn10k_ddr_perf_free_counter(pmu, counter);
540 	/* Reset previous count as h/w counter are reset */
653 	/* Setup the PMU counter to work in manual mode */