perf/hisilicon/hisi_uncore_uc_pmu.c

79 	u32 val;
84 	val = readl(uc_pmu->base + HISI_UC_TRACETAG_CTRL_REG);
87 	if (FIELD_GET(HISI_UC_TRACETAG_REQ_MSK, val) == HISI_UC_RD_REQ_TRACETAG)
91 	val &= ~HISI_UC_TRACETAG_REQ_MSK;
92 	val |= FIELD_PREP(HISI_UC_TRACETAG_REQ_MSK, HISI_UC_RD_REQ_TRACETAG);
93 	val |= HISI_UC_TRACETAG_REQ_EN;
94 	writel(val, uc_pmu->base + HISI_UC_TRACETAG_CTRL_REG);
100 	u32 val;
105 	val = readl(uc_pmu->base + HISI_UC_TRACETAG_CTRL_REG);
108 	if (FIELD_GET(HISI_UC_TRACETAG_REQ_MSK, val) == 0)
112 	val &= ~HISI_UC_TRACETAG_REQ_MSK;
113 	val &= ~HISI_UC_TRACETAG_REQ_EN;
114 	writel(val, uc_pmu->base + HISI_UC_TRACETAG_CTRL_REG);
120 	u32 val;
125 	val = readl(uc_pmu->base + HISI_UC_TRACETAG_CTRL_REG);
128 	if (FIELD_GET(HISI_UC_TRACETAG_SRCID_EN, val))
132 	val |= HISI_UC_TRACETAG_SRCID_EN;
133 	writel(val, uc_pmu->base + HISI_UC_TRACETAG_CTRL_REG);
135 	val = readl(uc_pmu->base + HISI_UC_SRCID_CTRL_REG);
136 	val &= ~HISI_UC_SRCID_MSK;
137 	val |= FIELD_PREP(HISI_UC_SRCID_MSK, hisi_get_srcid(event));
138 	writel(val, uc_pmu->base + HISI_UC_SRCID_CTRL_REG);
147 	u32 val;
152 	val = readl(uc_pmu->base + HISI_UC_TRACETAG_CTRL_REG);
155 	if (FIELD_GET(HISI_UC_TRACETAG_SRCID_EN, val) == 0)
161 	val &= ~HISI_UC_TRACETAG_SRCID_EN;
162 	writel(val, uc_pmu->base + HISI_UC_TRACETAG_CTRL_REG);
164 	val = readl(uc_pmu->base + HISI_UC_SRCID_CTRL_REG);
165 	val &= ~HISI_UC_SRCID_MSK;
166 	writel(val, uc_pmu->base + HISI_UC_SRCID_CTRL_REG);
173 	u32 val;
179 	val = readl(uc_pmu->base + HISI_UC_EVENT_CTRL_REG);
182 	if (uring_channel == FIELD_GET(HISI_UC_EVENT_URING_MSK, val))
185 	val &= ~HISI_UC_EVENT_URING_MSK;
186 	val |= FIELD_PREP(HISI_UC_EVENT_URING_MSK, uring_channel);
187 	writel(val, uc_pmu->base + HISI_UC_EVENT_CTRL_REG);
193 	u32 val;
199 	val = readl(uc_pmu->base + HISI_UC_EVENT_CTRL_REG);
202 	if (FIELD_GET(HISI_UC_EVENT_URING_MSK, val) == 0)
205 	val &= ~HISI_UC_EVENT_URING_MSK;
206 	writel(val, uc_pmu->base + HISI_UC_EVENT_CTRL_REG);
231 	u32 val;
238 	val = readl(uc_pmu->base + HISI_UC_EVTYPE_REGn(idx / 4));
239 	val &= ~(HISI_UC_EVTYPE_MASK << HISI_PMU_EVTYPE_SHIFT(idx));
240 	val |= (type << HISI_PMU_EVTYPE_SHIFT(idx));
241 	writel(val, uc_pmu->base + HISI_UC_EVTYPE_REGn(idx / 4));
246 	u32 val;
248 	val = readl(uc_pmu->base + HISI_UC_EVENT_CTRL_REG);
249 	val |= HISI_UC_EVENT_GLB_EN;
250 	writel(val, uc_pmu->base + HISI_UC_EVENT_CTRL_REG);
255 	u32 val;
257 	val = readl(uc_pmu->base + HISI_UC_EVENT_CTRL_REG);
258 	val &= ~HISI_UC_EVENT_GLB_EN;
259 	writel(val, uc_pmu->base + HISI_UC_EVENT_CTRL_REG);
265 	u32 val;
268 	val = readl(uc_pmu->base + HISI_UC_EVENT_CTRL_REG);
269 	val |= (1 << hwc->idx);
270 	writel(val, uc_pmu->base + HISI_UC_EVENT_CTRL_REG);
276 	u32 val;
279 	val = readl(uc_pmu->base + HISI_UC_EVENT_CTRL_REG);
280 	val &= ~(1 << hwc->idx);
281 	writel(val, uc_pmu->base + HISI_UC_EVENT_CTRL_REG);
292 	u32 val;
294 	val = readl(uc_pmu->base + HISI_UC_EVENT_CTRL_REG);
295 	return !!FIELD_GET(HISI_UC_EVENT_GLB_EN, val);
299 				      struct hw_perf_event *hwc, u64 val)
301 	writeq(val, uc_pmu->base + HISI_UC_CNTR_REGn(hwc->idx));
305 				      struct hw_perf_event *hwc, u64 val)
308 	hisi_uc_pmu_write_counter_normal(uc_pmu, hwc, val);
313 				      struct hw_perf_event *hwc, u64 val)
331 		hisi_uc_pmu_write_counter_normal(uc_pmu, hwc, val);
333 		hisi_uc_pmu_write_counter_quirk_v2(uc_pmu, hwc, val);
339 	u32 val;
341 	val = readl(uc_pmu->base + HISI_UC_INT_MASK_REG);
342 	val &= ~(1 << hwc->idx);
343 	writel(val, uc_pmu->base + HISI_UC_INT_MASK_REG);
349 	u32 val;
351 	val = readl(uc_pmu->base + HISI_UC_INT_MASK_REG);
352 	val |= (1 << hwc->idx);
353 	writel(val, uc_pmu->base + HISI_UC_INT_MASK_REG);