perf/hisilicon/hisi_uncore_pmu.c

186 	struct hw_perf_event *hwc = &event->hw;
225 	hwc->idx		= -1;
226 	hwc->config_base	= event->attr.config;
245 	struct hw_perf_event *hwc = &event->hw;
247 	hisi_pmu->ops->write_evtype(hisi_pmu, hwc->idx,
253 	hisi_pmu->ops->enable_counter_int(hisi_pmu, hwc);
254 	hisi_pmu->ops->enable_counter(hisi_pmu, hwc);
263 	struct hw_perf_event *hwc = &event->hw;
265 	hisi_pmu->ops->disable_counter(hisi_pmu, hwc);
266 	hisi_pmu->ops->disable_counter_int(hisi_pmu, hwc);
275 	struct hw_perf_event *hwc = &event->hw;
286 	local64_set(&hwc->prev_count, val);
288 	hisi_pmu->ops->write_counter(hisi_pmu, hwc, val);
295 	struct hw_perf_event *hwc = &event->hw;
300 		new_raw_count = hisi_pmu->ops->read_counter(hisi_pmu, hwc);
301 		prev_raw_count = local64_read(&hwc->prev_count);
302 	} while (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
316 	struct hw_perf_event *hwc = &event->hw;
318 	if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
321 	WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
322 	hwc->state = 0;
326 		u64 prev_raw_count =  local64_read(&hwc->prev_count);
328 		hisi_pmu->ops->write_counter(hisi_pmu, hwc, prev_raw_count);
338 	struct hw_perf_event *hwc = &event->hw;
341 	WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
342 	hwc->state |= PERF_HES_STOPPED;
344 	if (hwc->state & PERF_HES_UPTODATE)
349 	hwc->state |= PERF_HES_UPTODATE;
356 	struct hw_perf_event *hwc = &event->hw;
359 	hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
379 	struct hw_perf_event *hwc = &event->hw;
382 	hisi_uncore_pmu_clear_event_idx(hisi_pmu, hwc->idx);
384 	hisi_pmu->pmu_events.hw_events[hwc->idx] = NULL;