perf/hisilicon/hisi_uncore_ddrc_pmu.c

81 static u64 hisi_ddrc_pmu_v1_read_counter(struct hisi_pmu *ddrc_pmu,
84 	return readl(ddrc_pmu->base +
88 static void hisi_ddrc_pmu_v1_write_counter(struct hisi_pmu *ddrc_pmu,
92 	       ddrc_pmu->base + hisi_ddrc_pmu_v1_get_counter_offset(hwc->idx));
95 static u64 hisi_ddrc_pmu_v2_read_counter(struct hisi_pmu *ddrc_pmu,
98 	return readq(ddrc_pmu->base +
102 static void hisi_ddrc_pmu_v2_write_counter(struct hisi_pmu *ddrc_pmu,
106 	       ddrc_pmu->base + hisi_ddrc_pmu_v2_get_counter_offset(hwc->idx));
125 static void hisi_ddrc_pmu_v1_start_counters(struct hisi_pmu *ddrc_pmu)
130 	val = readl(ddrc_pmu->base + DDRC_PERF_CTRL);
132 	writel(val, ddrc_pmu->base + DDRC_PERF_CTRL);
135 static void hisi_ddrc_pmu_v1_stop_counters(struct hisi_pmu *ddrc_pmu)
140 	val = readl(ddrc_pmu->base + DDRC_PERF_CTRL);
142 	writel(val, ddrc_pmu->base + DDRC_PERF_CTRL);
145 static void hisi_ddrc_pmu_v1_enable_counter(struct hisi_pmu *ddrc_pmu,
151 	val = readl(ddrc_pmu->base + DDRC_EVENT_CTRL);
153 	writel(val, ddrc_pmu->base + DDRC_EVENT_CTRL);
156 static void hisi_ddrc_pmu_v1_disable_counter(struct hisi_pmu *ddrc_pmu,
162 	val = readl(ddrc_pmu->base + DDRC_EVENT_CTRL);
164 	writel(val, ddrc_pmu->base + DDRC_EVENT_CTRL);
169 	struct hisi_pmu *ddrc_pmu = to_hisi_pmu(event->pmu);
170 	unsigned long *used_mask = ddrc_pmu->pmu_events.used_mask;
188 static void hisi_ddrc_pmu_v2_start_counters(struct hisi_pmu *ddrc_pmu)
192 	val = readl(ddrc_pmu->base + DDRC_V2_PERF_CTRL);
194 	writel(val, ddrc_pmu->base + DDRC_V2_PERF_CTRL);
197 static void hisi_ddrc_pmu_v2_stop_counters(struct hisi_pmu *ddrc_pmu)
201 	val = readl(ddrc_pmu->base + DDRC_V2_PERF_CTRL);
203 	writel(val, ddrc_pmu->base + DDRC_V2_PERF_CTRL);
206 static void hisi_ddrc_pmu_v2_enable_counter(struct hisi_pmu *ddrc_pmu,
211 	val = readl(ddrc_pmu->base + DDRC_V2_EVENT_CTRL);
213 	writel(val, ddrc_pmu->base + DDRC_V2_EVENT_CTRL);
216 static void hisi_ddrc_pmu_v2_disable_counter(struct hisi_pmu *ddrc_pmu,
221 	val = readl(ddrc_pmu->base + DDRC_V2_EVENT_CTRL);
223 	writel(val, ddrc_pmu->base + DDRC_V2_EVENT_CTRL);
226 static void hisi_ddrc_pmu_v1_enable_counter_int(struct hisi_pmu *ddrc_pmu,
232 	val = readl(ddrc_pmu->base + DDRC_INT_MASK);
234 	writel(val, ddrc_pmu->base + DDRC_INT_MASK);
237 static void hisi_ddrc_pmu_v1_disable_counter_int(struct hisi_pmu *ddrc_pmu,
243 	val = readl(ddrc_pmu->base + DDRC_INT_MASK);
245 	writel(val, ddrc_pmu->base + DDRC_INT_MASK);
248 static void hisi_ddrc_pmu_v2_enable_counter_int(struct hisi_pmu *ddrc_pmu,
253 	val = readl(ddrc_pmu->base + DDRC_V2_INT_MASK);
255 	writel(val, ddrc_pmu->base + DDRC_V2_INT_MASK);
258 static void hisi_ddrc_pmu_v2_disable_counter_int(struct hisi_pmu *ddrc_pmu,
263 	val = readl(ddrc_pmu->base + DDRC_V2_INT_MASK);
265 	writel(val, ddrc_pmu->base + DDRC_V2_INT_MASK);
268 static u32 hisi_ddrc_pmu_v1_get_int_status(struct hisi_pmu *ddrc_pmu)
270 	return readl(ddrc_pmu->base + DDRC_INT_STATUS);
273 static void hisi_ddrc_pmu_v1_clear_int_status(struct hisi_pmu *ddrc_pmu,
276 	writel(1 << idx, ddrc_pmu->base + DDRC_INT_CLEAR);
279 static u32 hisi_ddrc_pmu_v2_get_int_status(struct hisi_pmu *ddrc_pmu)
281 	return readl(ddrc_pmu->base + DDRC_V2_INT_STATUS);
284 static void hisi_ddrc_pmu_v2_clear_int_status(struct hisi_pmu *ddrc_pmu,
287 	writel(1 << idx, ddrc_pmu->base + DDRC_V2_INT_CLEAR);
298 				   struct hisi_pmu *ddrc_pmu)
305 				     &ddrc_pmu->index_id)) {
311 				     &ddrc_pmu->sccl_id)) {
316 	ddrc_pmu->ccl_id = -1;
318 	ddrc_pmu->base = devm_platform_ioremap_resource(pdev, 0);
319 	if (IS_ERR(ddrc_pmu->base)) {
320 		dev_err(&pdev->dev, "ioremap failed for ddrc_pmu resource\n");
321 		return PTR_ERR(ddrc_pmu->base);
324 	ddrc_pmu->identifier = readl(ddrc_pmu->base + DDRC_VERSION);
325 	if (ddrc_pmu->identifier >= HISI_PMU_V2) {
327 					     &ddrc_pmu->sub_id)) {
455 				   struct hisi_pmu *ddrc_pmu)
459 	ret = hisi_ddrc_pmu_init_data(pdev, ddrc_pmu);
463 	ret = hisi_uncore_pmu_init_irq(ddrc_pmu, pdev);
467 	if (ddrc_pmu->identifier >= HISI_PMU_V2) {
468 		ddrc_pmu->counter_bits = 48;
469 		ddrc_pmu->check_event = DDRC_V2_NR_EVENTS;
470 		ddrc_pmu->pmu_events.attr_groups = hisi_ddrc_pmu_v2_attr_groups;
471 		ddrc_pmu->ops = &hisi_uncore_ddrc_v2_ops;
473 		ddrc_pmu->counter_bits = 32;
474 		ddrc_pmu->check_event = DDRC_V1_NR_EVENTS;
475 		ddrc_pmu->pmu_events.attr_groups = hisi_ddrc_pmu_v1_attr_groups;
476 		ddrc_pmu->ops = &hisi_uncore_ddrc_v1_ops;
479 	ddrc_pmu->num_counters = DDRC_NR_COUNTERS;
480 	ddrc_pmu->dev = &pdev->dev;
481 	ddrc_pmu->on_cpu = -1;
488 	struct hisi_pmu *ddrc_pmu;
492 	ddrc_pmu = devm_kzalloc(&pdev->dev, sizeof(*ddrc_pmu), GFP_KERNEL);
493 	if (!ddrc_pmu)
496 	platform_set_drvdata(pdev, ddrc_pmu);
498 	ret = hisi_ddrc_pmu_dev_probe(pdev, ddrc_pmu);
502 	if (ddrc_pmu->identifier >= HISI_PMU_V2)
505 				      ddrc_pmu->sccl_id, ddrc_pmu->index_id,
506 				      ddrc_pmu->sub_id);
509 				      "hisi_sccl%u_ddrc%u", ddrc_pmu->sccl_id,
510 				      ddrc_pmu->index_id);
516 				       &ddrc_pmu->node);
522 	hisi_pmu_init(ddrc_pmu, THIS_MODULE);
524 	ret = perf_pmu_register(&ddrc_pmu->pmu, name, -1);
526 		dev_err(ddrc_pmu->dev, "DDRC PMU register failed!\n");
528 			CPUHP_AP_PERF_ARM_HISI_DDRC_ONLINE, &ddrc_pmu->node);
536 	struct hisi_pmu *ddrc_pmu = platform_get_drvdata(pdev);
538 	perf_pmu_unregister(&ddrc_pmu->pmu);
540 					    &ddrc_pmu->node);