Lines Matching refs:IMX9_DDR_PMU_EVENT_ATTR
130 #define IMX9_DDR_PMU_EVENT_ATTR(_name, _id) \
138 IMX9_DDR_PMU_EVENT_ATTR(cycles, 0),
141 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ddrc1_rmw_for_ecc, 12),
142 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_rreorder, 13),
143 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_wreorder, 14),
144 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_0, 15),
145 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_1, 16),
146 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_2, 17),
147 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_3, 18),
148 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_4, 19),
149 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_5, 22),
150 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_6, 23),
151 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_7, 24),
152 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_8, 25),
153 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_9, 26),
154 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_10, 27),
155 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_11, 28),
156 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_12, 31),
157 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_13, 59),
158 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_15, 61),
159 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_29, 63),
162 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_0, 64),
163 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_1, 65),
164 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_2, 66),
165 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_3, 67),
166 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_4, 68),
167 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_5, 69),
168 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_6, 70),
169 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_7, 71),
172 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_0, 64),
173 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_1, 65),
174 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_2, 66),
175 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_3, 67),
176 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_4, 68),
177 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_5, 69),
178 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_6, 70),
179 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_7, 71),
180 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_empty, 72),
181 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_trans_filt, 73),
184 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_0, 64),
185 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_1, 65),
186 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_2, 66),
187 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_3, 67),
188 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_4, 68),
189 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_5, 69),
190 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_6, 70),
191 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_7, 71),
192 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_full, 72),
193 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_trans_filt, 73),
196 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_0, 64),
197 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_1, 65),
198 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_2, 66),
199 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_3, 67),
200 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_4, 68),
201 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_5, 69),
202 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_6, 70),
203 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_7, 71),
204 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq2_rmw, 72),
205 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt, 73),
208 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_0, 64),
209 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_1, 65),
210 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_2, 66),
211 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_3, 67),
212 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_4, 68),
213 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_5, 69),
214 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_6, 70),
215 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_7, 71),
216 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq1, 72),
219 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_end_0, 64),
220 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq2, 72),
223 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_1_2_full, 64),
224 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_wrq0, 65),
227 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_bias_switched, 64),
228 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_1_4_full, 65),
231 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_wrq1, 65),
232 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_3_4_full, 66),
235 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_misc_mrk, 65),
236 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq0, 66),