drivers/perf/fsl_imx9_ddr_perf.c

32  * 32bit counters monitor counter-specific events in addition to counting reference events
246 PMU_FORMAT_ATTR(counter, "config:8-15");
271 static void ddr_perf_clear_counter(struct ddr_pmu *pmu, int counter)
273 	if (counter == CYCLES_COUNTER) {
274 		writel(0, pmu->base + PMC(counter) + 0x4);
275 		writel(0, pmu->base + PMC(counter));
277 		writel(0, pmu->base + PMC(counter));
281 static u64 ddr_perf_read_counter(struct ddr_pmu *pmu, int counter)
286 	if (counter != CYCLES_COUNTER) {
287 		val = readl_relaxed(pmu->base + PMC(counter));
291 	/* special handling for reading 64bit cycle counter */
293 		val_upper = readl_relaxed(pmu->base + PMC(counter) + 0x4);
294 		val_lower = readl_relaxed(pmu->base + PMC(counter));
295 	} while (val_upper != readl_relaxed(pmu->base + PMC(counter) + 0x4));
339 				    int counter, bool enable)
343 	ctrl_a = readl_relaxed(pmu->base + PMLCA(counter));
347 		writel(ctrl_a, pmu->base + PMLCA(counter));
349 		ddr_perf_clear_counter(pmu, counter);
351 		/* Freeze counter disabled, condition enabled, and program event.*/
356 		writel(ctrl_a, pmu->base + PMLCA(counter));
358 		/* Freeze counter. */
360 		writel(ctrl_a, pmu->base + PMLCA(counter));
367 	int event, counter;
370 	counter = (cfg & 0x0000FF00) >> 8;
374 	if (counter == 2 && event == 73)
376 	else if (counter == 2 && event != 73)
379 	if (counter == 3 && event == 73)
381 	else if (counter == 3 && event != 73)
384 	if (counter == 4 && event == 73)
386 	else if (counter == 4 && event != 73)
403 	int counter = hwc->idx;
406 	new_raw_count = ddr_perf_read_counter(pmu, counter);
409 	/* clear counter's value every time */
410 	ddr_perf_clear_counter(pmu, counter);
455 	int counter = hwc->idx;
459 	ddr_perf_counter_local_config(pmu, event->attr.config, counter, true);
470 	int counter;
472 	counter = (cfg & 0x0000FF00) >> 8;
474 	pmu->events[counter] = event;
476 	hwc->idx = counter;
492 	int counter = hwc->idx;
494 	ddr_perf_counter_local_config(pmu, event->attr.config, counter, false);
556 	 * counter changes from 0 to 1. For the interrupt to be signalled,
562 	 * monitor and clearing the most significant bit of the counter that