Lines Matching defs:hwc
114 struct hw_perf_event *hwc, u32 filter);
660 struct hw_perf_event *hwc = &event->hw;
708 hwc->idx = -1;
709 hwc->extra_reg.idx = -1;
710 hwc->config = cspmu->impl.ops.event_type(event);
804 struct hw_perf_event *hwc = &event->hw;
808 prev = local64_read(&hwc->prev_count);
810 } while (local64_cmpxchg(&hwc->prev_count, prev, now) != prev);
817 struct hw_perf_event *hwc)
819 u32 offset = PMEVTYPER + (4 * hwc->idx);
821 writel(hwc->config, cspmu->base0 + offset);
825 struct hw_perf_event *hwc,
828 u32 offset = PMEVFILTR + (4 * hwc->idx);
843 struct hw_perf_event *hwc = &event->hw;
848 WARN_ON(!(hwc->state & PERF_HES_UPTODATE));
857 arm_cspmu_set_event(cspmu, hwc);
858 cspmu->impl.ops.set_ev_filter(cspmu, hwc, filter);
861 hwc->state = 0;
863 arm_cspmu_enable_counter(cspmu, hwc->idx);
869 struct hw_perf_event *hwc = &event->hw;
871 if (hwc->state & PERF_HES_STOPPED)
874 arm_cspmu_disable_counter(cspmu, hwc->idx);
877 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
890 struct hw_perf_event *hwc = &event->hw;
902 hwc->idx = to_phys_idx(cspmu, idx);
903 hwc->extra_reg.idx = idx;
904 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
919 struct hw_perf_event *hwc = &event->hw;
920 int idx = hwc->extra_reg.idx;