drivers/perf/arm-cmn.c

285 	s8 dtc;
346 	struct arm_cmn_dtc *dtc;
541 			s8 dtc = cmn->xps[xp_base + x].dtc;
543 			if (dtc < 0)
546 				seq_printf(s, " DTC %d  |", dtc);
1370 		writel_relaxed(0, cmn->dtc[0].base + CMN_DT_PMCR);
1379 			       cmn->dtc[0].base + CMN_DT_PMCR);
1412 static u64 arm_cmn_read_cc(struct arm_cmn_dtc *dtc)
1414 	u64 val = readq_relaxed(dtc->base + CMN_DT_PMCCNTR);
1416 	writeq_relaxed(CMN_CC_INIT, dtc->base + CMN_DT_PMCCNTR);
1420 static u32 arm_cmn_read_counter(struct arm_cmn_dtc *dtc, int idx)
1424 	val = readl_relaxed(dtc->base + pmevcnt);
1425 	writel_relaxed(CMN_COUNTER_INIT, dtc->base + pmevcnt);
1436 		writel_relaxed(CMN_COUNTER_INIT, cmn->dtc[i].base + CMN_DT_PMEVCNT(idx));
1437 		cmn->dtc[i].counters[idx] = event;
1452 		delta = arm_cmn_read_cc(cmn->dtc + hw->dtc_idx[0]);
1463 		new = arm_cmn_read_counter(cmn->dtc + i, idx);
1520 		writeq_relaxed(CMN_CC_INIT, cmn->dtc[i].base + CMN_DT_PMCCNTR);
1521 		cmn->dtc[i].cc_active = true;
1551 		cmn->dtc[i].cc_active = false;
1595 	for_each_hw_dtc_idx(hw, dtc, idx)
1596 		val->dtc_count[dtc]++;
1746 		if (dn->dtc < 0)
1749 			hw->dtc_idx[dn->dtc] = 0;
1788 		cmn->dtc[j].counters[idx] = NULL;
1800 		while (cmn->dtc[i].cycles)
1804 		cmn->dtc[i].cycles = event;
1818 			while (cmn->dtc[j].counters[idx])
1828 		unsigned int dtm_idx, shift, d = max_t(int, dn->dtc, 0);
1847 					CMN_EVENT_WP_COMBINE(cmn->dtc[d].counters[tmp]))
1899 		cmn->dtc[hw->dtc_idx[0]].cycles = NULL;
1932 		irq_set_affinity(cmn->dtc[i].irq, cpumask_of(cpu));
1972 	struct arm_cmn_dtc *dtc = dev_id;
1976 		u32 status = readl_relaxed(dtc->base + CMN_DT_PMOVSR);
1983 				if (WARN_ON(!dtc->counters[i]))
1985 				delta = (u64)arm_cmn_read_counter(dtc, i) << 16;
1986 				local64_add(delta, &dtc->counters[i]->count);
1992 			if (dtc->cc_active && !WARN_ON(!dtc->cycles)) {
1993 				delta = arm_cmn_read_cc(dtc);
1994 				local64_add(delta, &dtc->cycles->count);
1998 		writel_relaxed(status, dtc->base + CMN_DT_PMOVSR_CLR);
2000 		if (!dtc->irq_friend)
2002 		dtc += dtc->irq_friend;
2012 		irq = cmn->dtc[i].irq;
2014 			if (cmn->dtc[j].irq == irq) {
2015 				cmn->dtc[j].irq_friend = i - j;
2021 				       dev_name(cmn->dev), &cmn->dtc[i]);
2050 	struct arm_cmn_dtc *dtc = cmn->dtc + idx;
2052 	dtc->base = dn->pmu_base - CMN_PMU_OFFSET;
2053 	dtc->irq = platform_get_irq(to_platform_device(cmn->dev), idx);
2054 	if (dtc->irq < 0)
2055 		return dtc->irq;
2057 	writel_relaxed(CMN_DT_DTC_CTL_DT_EN, dtc->base + CMN_DT_DTC_CTL);
2058 	writel_relaxed(CMN_DT_PMCR_PMU_EN | CMN_DT_PMCR_OVFL_INTR_EN, dtc->base + CMN_DT_PMCR);
2059 	writeq_relaxed(0, dtc->base + CMN_DT_PMCCNTR);
2060 	writel_relaxed(0x1ff, dtc->base + CMN_DT_PMOVSR_CLR);
2081 	cmn->dtc = devm_kcalloc(cmn->dev, cmn->num_dtcs, sizeof(cmn->dtc[0]), GFP_KERNEL);
2082 	if (!cmn->dtc)
2093 			arm_cmn_node_to_xp(cmn, dn + i)->dtc = i;
2101 		dn->dtc = xp->dtc;
2266 			xp->dtc = -1;
2268 			xp->dtc = arm_cmn_dtc_domain(cmn, xp_region);
2523 	writel_relaxed(0, cmn->dtc[0].base + CMN_DT_DTC_CTL);