Lines Matching refs:pdev
81 static bool dpc_completed(struct pci_dev *pdev)
85 pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_STATUS, &status);
89 if (test_bit(PCI_DPC_RECOVERING, &pdev->priv_flags))
97 * @pdev: PCI device
99 * Return true if DPC was triggered for @pdev and has recovered successfully.
103 bool pci_dpc_recovered(struct pci_dev *pdev)
107 if (!pdev->dpc_cap)
114 host = pci_find_host_bridge(pdev->bus);
123 wait_event_timeout(dpc_completed_waitqueue, dpc_completed(pdev),
126 return test_and_clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);
130 static int dpc_wait_rp_inactive(struct pci_dev *pdev)
133 u16 cap = pdev->dpc_cap, status;
135 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
139 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
142 pci_warn(pdev, "root port still busy\n");
148 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev)
153 set_bit(PCI_DPC_RECOVERING, &pdev->priv_flags);
159 cap = pdev->dpc_cap;
165 if (!pcie_wait_for_link(pdev, false))
166 pci_info(pdev, "Data Link Layer Link Active not cleared in 1000 msec\n");
168 if (pdev->dpc_rp_extensions && dpc_wait_rp_inactive(pdev)) {
169 clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);
174 pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,
177 if (pci_bridge_wait_for_secondary_bus(pdev, "DPC")) {
178 clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);
181 set_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);
185 clear_bit(PCI_DPC_RECOVERING, &pdev->priv_flags);
190 static void dpc_process_rp_pio_error(struct pci_dev *pdev)
192 u16 cap = pdev->dpc_cap, dpc_status, first_error;
197 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, &status);
198 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_MASK, &mask);
199 pci_err(pdev, "rp_pio_status: %#010x, rp_pio_mask: %#010x\n",
202 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SEVERITY, &sev);
203 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SYSERROR, &syserr);
204 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_EXCEPTION, &exc);
205 pci_err(pdev, "RP PIO severity=%#010x, syserror=%#010x, exception=%#010x\n",
209 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &dpc_status);
214 pci_err(pdev, "[%2d] %s%s\n", i, rp_pio_error_string[i],
218 if (pdev->dpc_rp_log_size < 4)
220 pcie_read_tlp_log(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG, &tlp_log);
221 pci_err(pdev, "TLP Header: %#010x %#010x %#010x %#010x\n",
224 if (pdev->dpc_rp_log_size < 5)
226 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG, &log);
227 pci_err(pdev, "RP PIO ImpSpec Log %#010x\n", log);
229 for (i = 0; i < pdev->dpc_rp_log_size - 5; i++) {
230 pci_read_config_dword(pdev,
232 pci_err(pdev, "TLP Prefix Header: dw%d, %#010x\n", i, prefix);
235 pci_write_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, status);
260 void dpc_process_error(struct pci_dev *pdev)
262 u16 cap = pdev->dpc_cap, status, source, reason, ext_reason;
265 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
266 pci_read_config_word(pdev, cap + PCI_EXP_DPC_SOURCE_ID, &source);
268 pci_info(pdev, "containment event, status:%#06x source:%#06x\n",
273 pci_warn(pdev, "%s detected\n",
287 if (pdev->dpc_rp_extensions &&
290 dpc_process_rp_pio_error(pdev);
292 dpc_get_aer_uncorrect_severity(pdev, &info) &&
293 aer_get_device_error_info(pdev, &info)) {
294 aer_print_error(pdev, &info);
295 pci_aer_clear_nonfatal_status(pdev);
296 pci_aer_clear_fatal_status(pdev);
300 static void pci_clear_surpdn_errors(struct pci_dev *pdev)
302 if (pdev->dpc_rp_extensions)
303 pci_write_config_dword(pdev, pdev->dpc_cap +
311 pci_write_config_word(pdev, PCI_STATUS, 0xffff);
313 pcie_capability_write_word(pdev, PCI_EXP_DEVSTA, PCI_EXP_DEVSTA_FED);
316 static void dpc_handle_surprise_removal(struct pci_dev *pdev)
318 if (!pcie_wait_for_link(pdev, false)) {
319 pci_info(pdev, "Data Link Layer Link Active not cleared in 1000 msec\n");
323 if (pdev->dpc_rp_extensions && dpc_wait_rp_inactive(pdev))
326 pci_aer_raw_clear_status(pdev);
327 pci_clear_surpdn_errors(pdev);
329 pci_write_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_STATUS,
333 clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);
337 static bool dpc_is_surprise_removal(struct pci_dev *pdev)
341 if (!pdev->is_hotplug_bridge)
344 if (pci_read_config_word(pdev, pdev->aer_cap + PCI_ERR_UNCOR_STATUS,
353 struct pci_dev *pdev = context;
359 if (dpc_is_surprise_removal(pdev)) {
360 dpc_handle_surprise_removal(pdev);
364 dpc_process_error(pdev);
367 pcie_do_recovery(pdev, pci_channel_io_frozen, dpc_reset_link);
374 struct pci_dev *pdev = context;
375 u16 cap = pdev->dpc_cap, status;
377 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
382 pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,
389 void pci_dpc_init(struct pci_dev *pdev)
393 pdev->dpc_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DPC);
394 if (!pdev->dpc_cap)
397 pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CAP, &cap);
401 pdev->dpc_rp_extensions = true;
404 if (!pdev->dpc_rp_log_size) {
405 pdev->dpc_rp_log_size =
407 if (pdev->dpc_rp_log_size < 4 || pdev->dpc_rp_log_size > 9) {
408 pci_err(pdev, "RP PIO log size %u is invalid\n",
409 pdev->dpc_rp_log_size);
410 pdev->dpc_rp_log_size = 0;
418 struct pci_dev *pdev = dev->port;
423 if (!pcie_aer_is_native(pdev) && !pcie_ports_dpc_native)
428 "pcie-dpc", pdev);
430 pci_warn(pdev, "request IRQ%d failed: %d\n", dev->irq,
435 pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CAP, &cap);
437 pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, &ctl);
440 pci_write_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, ctl);
442 pci_info(pdev, "enabled with IRQ %d\n", dev->irq);
443 pci_info(pdev, "error containment capabilities: Int Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
446 FLAG(cap, PCI_EXP_DPC_CAP_SW_TRIGGER), pdev->dpc_rp_log_size,
449 pci_add_ext_cap_save_buffer(pdev, PCI_EXT_CAP_ID_DPC, sizeof(u16));
455 struct pci_dev *pdev = dev->port;
458 pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, &ctl);
460 pci_write_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, ctl);