drivers/pci/pci.c

314 		 * bridge because we hold a reference to the top level
315 		 * device which should hold a reference to the bridge,
814 			 * If we're below a transparent bridge, there may
877 		"bridge window",	/* "io" included in %pR */
878 		"bridge window",	/* "mem" included in %pR */
879 		"bridge window",	/* "mem pref" included in %pR */
896 		"CardBus bridge window 0",	/* I/O */
897 		"CardBus bridge window 1",	/* I/O */
898 		"CardBus bridge window 0",	/* mem */
899 		"CardBus bridge window 1",	/* mem */
1257 	struct pci_dev *bridge;
1260 		bridge = pci_upstream_bridge(dev);
1261 		if (bridge)
1293 				if (pcie_failed_link_retrain(bridge)) {
1556 		 * If the device or the parent bridge do not support PCI
1587 		/* Powering off a bridge may power off the whole hierarchy */
2010 	struct pci_dev *bridge;
2018 	bridge = pci_upstream_bridge(dev);
2019 	if (bridge)
2020 		pcie_aspm_powersave_config_link(bridge);
2058 	struct pci_dev *bridge;
2061 	bridge = pci_upstream_bridge(dev);
2062 	if (bridge)
2063 		pci_enable_bridge(bridge);
2073 		pci_err(dev, "Error enabling bridge (%d), continuing\n",
2080 	struct pci_dev *bridge;
2095 	bridge = pci_upstream_bridge(dev);
2096 	if (bridge)
2097 		pci_enable_bridge(bridge);
2383 			struct pci_dev *bridge = pdev->bus->self;
2385 			struct device *bdev = bridge ? &bridge->dev : NULL;
2389 			 * If we have a bridge, it should be in an active/D0
2399 				if (bridge->current_state != PCI_D0)
2798 		struct pci_dev *bridge = bus->self;
2800 		if (device_can_wakeup(&bridge->dev))
2807 	if (bus->bridge)
2808 		return device_can_wakeup(bus->bridge);
2970  * pci_bridge_d3_possible - Is it possible to put the bridge into D3
2971  * @bridge: Bridge to check
2973  * This function checks if it is possible to move the bridge to D3.
2976 bool pci_bridge_d3_possible(struct pci_dev *bridge)
2978 	if (!pci_is_pcie(bridge))
2981 	switch (pci_pcie_type(bridge)) {
2992 		if (bridge->is_hotplug_bridge && !pciehp_is_native(bridge))
2999 		if (bridge->is_thunderbolt)
3002 		/* Platform might know better if the bridge supports D3 */
3003 		if (platform_pci_bridge_d3(bridge))
3011 		if (bridge->is_hotplug_bridge)
3040 	    /* If it is a bridge it must be allowed to go to D3. */
3049  * pci_bridge_d3_update - Update bridge D3 capabilities
3052  * Update upstream bridge PM capabilities accordingly depending on if the
3059 	struct pci_dev *bridge;
3062 	bridge = pci_upstream_bridge(dev);
3063 	if (!bridge || !pci_bridge_d3_possible(bridge))
3067 	 * If D3 is currently allowed for the bridge, removing one of its
3070 	if (remove && bridge->bridge_d3)
3074 	 * If D3 is currently allowed for the bridge and a child is added or
3078 	 * If D3 is currently not allowed for the bridge, checking the device
3085 	 * If D3 is currently not allowed for the bridge, this may be caused
3090 	if (d3cold_ok && !bridge->bridge_d3)
3091 		pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold,
3094 	if (bridge->bridge_d3 != d3cold_ok) {
3095 		bridge->bridge_d3 = d3cold_ok;
3097 		pci_bridge_d3_update(bridge);
3106  * they handle.  It also updates upstream PCI bridge PM capabilities
3123  * they handle.  It also updates upstream PCI bridge PM capabilities
3492  * If @dev and its upstream bridge both support ARI, enable ARI in the
3493  * bridge.  Otherwise, disable ARI in the bridge.
3498 	struct pci_dev *bridge;
3503 	bridge = dev->bus->self;
3504 	if (!bridge)
3507 	pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3512 		pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
3514 		bridge->ari_enabled = 1;
3516 		pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
3518 		bridge->ari_enabled = 0;
3793 	struct pci_dev *bridge;
3824 		bridge = bus->self;
3826 		pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3828 		switch (pci_pcie_type(bridge)) {
3844 		if (pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM) {
3845 			pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2,
4736  * @dev: PCI bridge
4740  * side of the bridge are permitted after D3cold to D0 transition
4874  * pci_bridge_secondary_bus_reset - Reset the secondary bus on a PCI bridge.
4877  * Use the bridge control register to assert reset on the secondary bus.
5626  * pci_bus_error_reset - reset the bridge's subordinate bus
5627  * @bridge: The parent device that connects to the bus to reset
5633 int pci_bus_error_reset(struct pci_dev *bridge)
5635 	struct pci_bus *bus = bridge->subordinate;
5657 	return pci_bus_reset(bridge->subordinate, PCI_RESET_DO_RESET);
5832 	struct pci_host_bridge *bridge = pci_find_host_bridge(dev->bus);
5839 	 * size to the max packet size to keep the host bridge from
5851 	if (bridge->no_inc_mrrs) {
6171 	struct pci_dev *bridge;
6196 		bridge = bus->self;
6197 		if (bridge) {
6198 			pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
6204 			pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
6300 	struct pci_dev *bridge = dev->bus->self;
6303 	/* Propagate the "ignore hotplug" setting to the parent bridge. */
6304 	if (bridge)
6305 		bridge->ignore_hotplug = 1;
6500 		pci_warn(dev, "Can't reassign resources to host bridge\n");
6512 	 * Need to disable bridge's resource window,