pci/hotplug/shpchp_hpc.c

169 static void start_int_poll_timer(struct controller *ctrl, int sec);
170 static int hpc_check_cmd_status(struct controller *ctrl);
172 static inline u8 shpc_readb(struct controller *ctrl, int reg)
174 	return readb(ctrl->creg + reg);
177 static inline u16 shpc_readw(struct controller *ctrl, int reg)
179 	return readw(ctrl->creg + reg);
182 static inline void shpc_writew(struct controller *ctrl, int reg, u16 val)
184 	writew(val, ctrl->creg + reg);
187 static inline u32 shpc_readl(struct controller *ctrl, int reg)
189 	return readl(ctrl->creg + reg);
192 static inline void shpc_writel(struct controller *ctrl, int reg, u32 val)
194 	writel(val, ctrl->creg + reg);
197 static inline int shpc_indirect_read(struct controller *ctrl, int index,
201 	u32 cap_offset = ctrl->cap_offset;
202 	struct pci_dev *pdev = ctrl->pci_dev;
215 	struct controller *ctrl = from_timer(ctrl, t, poll_timer);
218 	shpc_isr(0, ctrl);
223 	start_int_poll_timer(ctrl, shpchp_poll_time);
229 static void start_int_poll_timer(struct controller *ctrl, int sec)
235 	ctrl->poll_timer.expires = jiffies + sec * HZ;
236 	add_timer(&ctrl->poll_timer);
239 static inline int is_ctrl_busy(struct controller *ctrl)
241 	u16 cmd_status = shpc_readw(ctrl, CMD_STATUS);
249 static inline int shpc_poll_ctrl_busy(struct controller *ctrl)
253 	if (!is_ctrl_busy(ctrl))
259 		if (!is_ctrl_busy(ctrl))
266 static inline int shpc_wait_cmd(struct controller *ctrl)
273 		rc = shpc_poll_ctrl_busy(ctrl);
275 		rc = wait_event_interruptible_timeout(ctrl->queue,
276 						!is_ctrl_busy(ctrl), timeout);
277 	if (!rc && is_ctrl_busy(ctrl)) {
279 		ctrl_err(ctrl, "Command not completed in 1000 msec\n");
282 		ctrl_info(ctrl, "Command was interrupted by a signal\n");
290 	struct controller *ctrl = slot->ctrl;
295 	mutex_lock(&slot->ctrl->cmd_lock);
297 	if (!shpc_poll_ctrl_busy(ctrl)) {
299 		ctrl_err(ctrl, "Controller is still busy after 1 sec\n");
306 	ctrl_dbg(ctrl, "%s: t_slot %x cmd %x\n", __func__, t_slot, cmd);
311 	shpc_writew(ctrl, CMD, temp_word);
316 	retval = shpc_wait_cmd(slot->ctrl);
320 	cmd_status = hpc_check_cmd_status(slot->ctrl);
322 		ctrl_err(ctrl, "Failed to issued command 0x%x (error code = %d)\n",
327 	mutex_unlock(&slot->ctrl->cmd_lock);
331 static int hpc_check_cmd_status(struct controller *ctrl)
334 	u16 cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F;
342 		ctrl_err(ctrl, "Switch opened!\n");
346 		ctrl_err(ctrl, "Invalid HPC command!\n");
350 		ctrl_err(ctrl, "Invalid bus speed/mode!\n");
362 	struct controller *ctrl = slot->ctrl;
363 	u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
386 	struct controller *ctrl = slot->ctrl;
387 	u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
411 	struct controller *ctrl = slot->ctrl;
412 	u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
421 	struct controller *ctrl = slot->ctrl;
422 	u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
432 	struct controller *ctrl = slot->ctrl;
434 	*prog_int = shpc_readb(ctrl, PROG_INTERFACE);
442 	struct controller *ctrl = slot->ctrl;
443 	u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
462 	ctrl_dbg(ctrl, "%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n",
488 	ctrl_dbg(ctrl, "Adapter speed = %d\n", *value);
494 	struct controller *ctrl = slot->ctrl;
495 	u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
538 static void hpc_release_ctlr(struct controller *ctrl)
546 	for (i = 0; i < ctrl->num_slots; i++) {
547 		slot_reg = shpc_readl(ctrl, SLOT_REG(i));
553 		shpc_writel(ctrl, SLOT_REG(i), slot_reg);
556 	cleanup_slots(ctrl);
561 	serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
565 	shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
568 		del_timer(&ctrl->poll_timer);
570 		free_irq(ctrl->pci_dev->irq, ctrl);
571 		pci_disable_msi(ctrl->pci_dev);
574 	iounmap(ctrl->creg);
575 	release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
584 		ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);
597 		ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);
610 		ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);
615 static int shpc_get_cur_bus_speed(struct controller *ctrl)
618 	struct pci_bus *bus = ctrl->pci_dev->subordinate;
620 	u16 sec_bus_reg = shpc_readw(ctrl, SEC_BUS_CONFIG);
621 	u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
687 	struct controller *ctrl = slot->ctrl;
690 	pi = shpc_readb(ctrl, PROG_INTERFACE);
743 		ctrl_err(ctrl, "%s: Write command failed!\n", __func__);
745 		shpc_get_cur_bus_speed(ctrl);
752 	struct controller *ctrl = (struct controller *)dev_id;
757 	intr_loc = shpc_readl(ctrl, INTR_LOC);
761 	ctrl_dbg(ctrl, "%s: intr_loc = %x\n", __func__, intr_loc);
768 		serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
771 		shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
773 		intr_loc2 = shpc_readl(ctrl, INTR_LOC);
774 		ctrl_dbg(ctrl, "%s: intr_loc2 = %x\n", __func__, intr_loc2);
783 		serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
785 		shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
787 		wake_up_interruptible(&ctrl->queue);
793 	for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
798 		slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
799 		ctrl_dbg(ctrl, "Slot %x with intr, slot register = %x\n",
803 			shpchp_handle_switch_change(hp_slot, ctrl);
806 			shpchp_handle_attention_button(hp_slot, ctrl);
809 			shpchp_handle_presence_change(hp_slot, ctrl);
812 			shpchp_handle_power_fault(hp_slot, ctrl);
816 		shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
821 		serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
823 		shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
829 static int shpc_get_max_bus_speed(struct controller *ctrl)
832 	struct pci_bus *bus = ctrl->pci_dev->subordinate;
834 	u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
835 	u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1);
836 	u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2);
869 	ctrl_dbg(ctrl, "Max bus speed = %d\n", bus_speed);
896 int shpc_init(struct controller *ctrl, struct pci_dev *pdev)
904 	ctrl->pci_dev = pdev;  /* pci_dev of the P2P bridge */
905 	ctrl_dbg(ctrl, "Hotplug Controller:\n");
910 		ctrl->mmio_base = pci_resource_start(pdev, 0);
911 		ctrl->mmio_size = pci_resource_len(pdev, 0);
913 		ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC);
914 		if (!ctrl->cap_offset) {
915 			ctrl_err(ctrl, "Cannot find PCI capability\n");
918 		ctrl_dbg(ctrl, " cap_offset = %x\n", ctrl->cap_offset);
920 		rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset);
922 			ctrl_err(ctrl, "Cannot read base_offset\n");
926 		rc = shpc_indirect_read(ctrl, 3, &tempdword);
928 			ctrl_err(ctrl, "Cannot read slot config\n");
932 		ctrl_dbg(ctrl, " num_slots (indirect) %x\n", num_slots);
935 			rc = shpc_indirect_read(ctrl, i, &tempdword);
937 				ctrl_err(ctrl, "Cannot read creg (index = %d)\n",
941 			ctrl_dbg(ctrl, " offset %d: value %x\n", i, tempdword);
944 		ctrl->mmio_base =
946 		ctrl->mmio_size = 0x24 + 0x4 * num_slots;
949 	ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
955 		ctrl_err(ctrl, "pci_enable_device failed\n");
959 	if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) {
960 		ctrl_err(ctrl, "Cannot reserve MMIO region\n");
965 	ctrl->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size);
966 	if (!ctrl->creg) {
967 		ctrl_err(ctrl, "Cannot remap MMIO region %lx @ %lx\n",
968 			 ctrl->mmio_size, ctrl->mmio_base);
969 		release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
973 	ctrl_dbg(ctrl, "ctrl->creg %p\n", ctrl->creg);
975 	mutex_init(&ctrl->crit_sect);
976 	mutex_init(&ctrl->cmd_lock);
979 	init_waitqueue_head(&ctrl->queue);
981 	ctrl->hpc_ops = &shpchp_hpc_ops;
984 	slot_config = shpc_readl(ctrl, SLOT_CONFIG);
985 	ctrl->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8;
986 	ctrl->num_slots = slot_config & SLOT_NUM;
987 	ctrl->first_slot = (slot_config & PSN) >> 16;
988 	ctrl->slot_num_inc = ((slot_config & UPDOWN) >> 29) ? 1 : -1;
991 	tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
992 	ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);
996 	shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
997 	tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
998 	ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);
1003 	for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
1004 		slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
1005 		ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n",
1012 		shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
1017 		timer_setup(&ctrl->poll_timer, int_poll_timeout, 0);
1018 		start_int_poll_timer(ctrl, 10);
1023 			ctrl_info(ctrl, "Can't get msi for the hotplug controller\n");
1024 			ctrl_info(ctrl, "Use INTx for the hotplug controller\n");
1029 		rc = request_irq(ctrl->pci_dev->irq, shpc_isr, IRQF_SHARED,
1030 				 MY_NAME, (void *)ctrl);
1031 		ctrl_dbg(ctrl, "request_irq %d (returns %d)\n",
1032 			 ctrl->pci_dev->irq, rc);
1034 			ctrl_err(ctrl, "Can't get irq %d for the hotplug controller\n",
1035 				 ctrl->pci_dev->irq);
1039 	ctrl_dbg(ctrl, "HPC at %s irq=%x\n", pci_name(pdev), pdev->irq);
1041 	shpc_get_max_bus_speed(ctrl);
1042 	shpc_get_cur_bus_speed(ctrl);
1047 	for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
1048 		slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
1049 		ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n",
1054 		shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
1058 		tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1061 		shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
1062 		tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1063 		ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);
1070 	iounmap(ctrl->creg);