Lines Matching defs:p_slot
86 struct slot *p_slot;
166 int shpchp_configure_device(struct slot *p_slot);
167 void shpchp_unconfigure_device(struct slot *p_slot);
228 static inline void amd_pogo_errata_save_misc_reg(struct slot *p_slot)
233 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);
235 p_slot->ctrl->pcix_misc2_reg = pcix_misc2_temp;
243 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
246 static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot)
255 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg);
258 ctrl_dbg(p_slot->ctrl,
262 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set);
266 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg);
269 ctrl_dbg(p_slot->ctrl, "Memory_Base_Limit[ RSE ] (W1C)\n");
271 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set);
274 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);
276 if (p_slot->ctrl->pcix_misc2_reg & SERRFATALENABLE_MASK)
281 if (p_slot->ctrl->pcix_misc2_reg & SERRNONFATALENABLE_MASK)
286 if (p_slot->ctrl->pcix_misc2_reg & PERRFLOODENABLE_MASK)
291 if (p_slot->ctrl->pcix_misc2_reg & PERRFATALENABLE_MASK)
296 if (p_slot->ctrl->pcix_misc2_reg & PERRNONFATALENABLE_MASK)
300 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);