pci/controller/pcie-xilinx-nwl.c

4  * Based on pcie-xilinx.c, pci-tegra.c
174 static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off)
176 	return readl(pcie->breg_base + off);
179 static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off)
181 	writel(val, pcie->breg_base + off);
184 static bool nwl_pcie_link_up(struct nwl_pcie *pcie)
186 	if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT)
191 static bool nwl_phy_link_up(struct nwl_pcie *pcie)
193 	if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT)
198 static int nwl_wait_for_link(struct nwl_pcie *pcie)
200 	struct device *dev = pcie->dev;
205 		if (nwl_phy_link_up(pcie))
216 	struct nwl_pcie *pcie = bus->sysdata;
220 		if (!nwl_pcie_link_up(pcie))
242 	struct nwl_pcie *pcie = bus->sysdata;
247 	return pcie->ecam_base + PCIE_ECAM_OFFSET(bus->number, devfn, where);
259 	struct nwl_pcie *pcie = data;
260 	struct device *dev = pcie->dev;
264 	misc_stat = nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
309 	nwl_bridge_writel(pcie, misc_stat, MSGF_MISC_STATUS);
317 	struct nwl_pcie *pcie;
322 	pcie = irq_desc_get_handler_data(desc);
324 	while ((status = nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
327 			generic_handle_domain_irq(pcie->intx_irq_domain, bit);
333 static void nwl_pcie_handle_msi_irq(struct nwl_pcie *pcie, u32 status_reg)
335 	struct nwl_msi *msi = &pcie->msi;
339 	while ((status = nwl_bridge_readl(pcie, status_reg)) != 0) {
341 			nwl_bridge_writel(pcie, 1 << bit, status_reg);
350 	struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);
353 	nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_HI);
360 	struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);
363 	nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_LO);
369 	struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
375 	raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);
376 	val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);
377 	nwl_bridge_writel(pcie, (val & (~mask)), MSGF_LEG_MASK);
378 	raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags);
383 	struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
389 	raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);
390 	val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);
391 	nwl_bridge_writel(pcie, (val | mask), MSGF_LEG_MASK);
392 	raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags);
436 	struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
437 	phys_addr_t msi_addr = pcie->phys_pcie_reg_base;
459 	struct nwl_pcie *pcie = domain->host_data;
460 	struct nwl_msi *msi = &pcie->msi;
485 	struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
486 	struct nwl_msi *msi = &pcie->msi;
499 static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie *pcie)
502 	struct device *dev = pcie->dev;
504 	struct nwl_msi *msi = &pcie->msi;
507 						&dev_msi_domain_ops, pcie);
524 static int nwl_pcie_init_irq_domain(struct nwl_pcie *pcie)
526 	struct device *dev = pcie->dev;
536 	pcie->intx_irq_domain = irq_domain_add_linear(intc_node,
539 						      pcie);
541 	if (!pcie->intx_irq_domain) {
546 	raw_spin_lock_init(&pcie->leg_mask_lock);
547 	nwl_pcie_init_msi_irq_domain(pcie);
551 static int nwl_pcie_enable_msi(struct nwl_pcie *pcie)
553 	struct device *dev = pcie->dev;
555 	struct nwl_msi *msi = &pcie->msi;
567 					 nwl_pcie_msi_handler_high, pcie);
575 					 nwl_pcie_msi_handler_low, pcie);
578 	ret = nwl_bridge_readl(pcie, I_MSII_CAPABILITIES) & MSII_PRESENT;
585 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
589 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
593 	base = pcie->phys_pcie_reg_base;
594 	nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO);
595 	nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI);
601 	nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_HI);
603 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie,  MSGF_MSI_STATUS_HI) &
606 	nwl_bridge_writel(pcie, MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI);
612 	nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_LO);
614 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO) &
617 	nwl_bridge_writel(pcie, MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO);
622 static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
624 	struct device *dev = pcie->dev;
629 	breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT;
636 	nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base),
638 	nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base),
642 	nwl_bridge_writel(pcie, ~BREG_ENABLE_FORCE & BREG_ENABLE,
646 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX0) |
650 	nwl_bridge_writel(pcie, SET_ISUB_CONTROL, I_ISUB_CONTROL);
653 	nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK,
658 		nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX1) |
661 	err = nwl_wait_for_link(pcie);
665 	ecam_val = nwl_bridge_readl(pcie, E_ECAM_CAPABILITIES) & E_ECAM_PRESENT;
672 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
675 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
679 	nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base),
681 	nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base),
684 	if (nwl_pcie_link_up(pcie))
690 	pcie->irq_misc = platform_get_irq_byname(pdev, "misc");
691 	if (pcie->irq_misc < 0)
694 	err = devm_request_irq(dev, pcie->irq_misc,
696 			       "nwl_pcie:misc", pcie);
699 			pcie->irq_misc);
704 	nwl_bridge_writel(pcie, (u32)~MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
707 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
711 	nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
714 	nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
717 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
721 	nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
724 	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_INTERRUPT) |
730 static int nwl_pcie_parse_dt(struct nwl_pcie *pcie,
733 	struct device *dev = pcie->dev;
737 	pcie->breg_base = devm_ioremap_resource(dev, res);
738 	if (IS_ERR(pcie->breg_base))
739 		return PTR_ERR(pcie->breg_base);
740 	pcie->phys_breg_base = res->start;
743 	pcie->pcireg_base = devm_ioremap_resource(dev, res);
744 	if (IS_ERR(pcie->pcireg_base))
745 		return PTR_ERR(pcie->pcireg_base);
746 	pcie->phys_pcie_reg_base = res->start;
749 	pcie->ecam_base = devm_pci_remap_cfg_resource(dev, res);
750 	if (IS_ERR(pcie->ecam_base))
751 		return PTR_ERR(pcie->ecam_base);
752 	pcie->phys_ecam_base = res->start;
755 	pcie->irq_intx = platform_get_irq_byname(pdev, "intx");
756 	if (pcie->irq_intx < 0)
757 		return pcie->irq_intx;
759 	irq_set_chained_handler_and_data(pcie->irq_intx,
760 					 nwl_pcie_leg_handler, pcie);
766 	{ .compatible = "xlnx,nwl-pcie-2.11", },
773 	struct nwl_pcie *pcie;
777 	bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
781 	pcie = pci_host_bridge_priv(bridge);
783 	pcie->dev = dev;
785 	err = nwl_pcie_parse_dt(pcie, pdev);
791 	pcie->clk = devm_clk_get(dev, NULL);
792 	if (IS_ERR(pcie->clk))
793 		return PTR_ERR(pcie->clk);
795 	err = clk_prepare_enable(pcie->clk);
801 	err = nwl_pcie_bridge_init(pcie);
807 	err = nwl_pcie_init_irq_domain(pcie);
813 	bridge->sysdata = pcie;
817 		err = nwl_pcie_enable_msi(pcie);
829 		.name = "nwl-pcie",