pci/controller/pcie-rockchip.c

33 	int err;
55 	err = rockchip_pcie_get_phys(rockchip);
56 	if (err)
57 		return err;
60 	err = of_property_read_u32(node, "num-lanes", &rockchip->lanes);
61 	if (!err && (rockchip->lanes == 0 ||
167 	int err, i;
170 	err = reset_control_assert(rockchip->aclk_rst);
171 	if (err) {
172 		dev_err(dev, "assert aclk_rst err %d\n", err);
173 		return err;
176 	err = reset_control_assert(rockchip->pclk_rst);
177 	if (err) {
178 		dev_err(dev, "assert pclk_rst err %d\n", err);
179 		return err;
182 	err = reset_control_assert(rockchip->pm_rst);
183 	if (err) {
184 		dev_err(dev, "assert pm_rst err %d\n", err);
185 		return err;
189 		err = phy_init(rockchip->phys[i]);
190 		if (err) {
191 			dev_err(dev, "init phy%d err %d\n", i, err);
196 	err = reset_control_assert(rockchip->core_rst);
197 	if (err) {
198 		dev_err(dev, "assert core_rst err %d\n", err);
202 	err = reset_control_assert(rockchip->mgmt_rst);
203 	if (err) {
204 		dev_err(dev, "assert mgmt_rst err %d\n", err);
208 	err = reset_control_assert(rockchip->mgmt_sticky_rst);
209 	if (err) {
210 		dev_err(dev, "assert mgmt_sticky_rst err %d\n", err);
214 	err = reset_control_assert(rockchip->pipe_rst);
215 	if (err) {
216 		dev_err(dev, "assert pipe_rst err %d\n", err);
222 	err = reset_control_deassert(rockchip->pm_rst);
223 	if (err) {
224 		dev_err(dev, "deassert pm_rst err %d\n", err);
228 	err = reset_control_deassert(rockchip->aclk_rst);
229 	if (err) {
230 		dev_err(dev, "deassert aclk_rst err %d\n", err);
234 	err = reset_control_deassert(rockchip->pclk_rst);
235 	if (err) {
236 		dev_err(dev, "deassert pclk_rst err %d\n", err);
258 		err = phy_power_on(rockchip->phys[i]);
259 		if (err) {
260 			dev_err(dev, "power on phy%d err %d\n", i, err);
265 	err = readx_poll_timeout(rockchip_pcie_read_addr,
270 	if (err) {
271 		dev_err(dev, "PHY PLLs could not lock, %d\n", err);
279 	err = reset_control_deassert(rockchip->mgmt_sticky_rst);
280 	if (err) {
281 		dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
285 	err = reset_control_deassert(rockchip->core_rst);
286 	if (err) {
287 		dev_err(dev, "deassert core_rst err %d\n", err);
291 	err = reset_control_deassert(rockchip->mgmt_rst);
292 	if (err) {
293 		dev_err(dev, "deassert mgmt_rst err %d\n", err);
297 	err = reset_control_deassert(rockchip->pipe_rst);
298 	if (err) {
299 		dev_err(dev, "deassert pipe_rst err %d\n", err);
311 	return err;
373 	int err;
375 	err = clk_prepare_enable(rockchip->aclk_pcie);
376 	if (err) {
378 		return err;
381 	err = clk_prepare_enable(rockchip->aclk_perf_pcie);
382 	if (err) {
387 	err = clk_prepare_enable(rockchip->hclk_pcie);
388 	if (err) {
393 	err = clk_prepare_enable(rockchip->clk_pcie_pm);
394 	if (err) {
407 	return err;