pci/controller/pcie-rockchip.c

75 			dev_err(dev, "missing core reset property in node\n");
82 			dev_err(dev, "missing mgmt reset property in node\n");
90 			dev_err(dev, "missing mgmt-sticky reset property in node\n");
97 			dev_err(dev, "missing pipe reset property in node\n");
104 			dev_err(dev, "missing pm reset property in node\n");
111 			dev_err(dev, "missing pclk reset property in node\n");
118 			dev_err(dev, "missing aclk reset property in node\n");
132 		dev_err(dev, "aclk clock not found\n");
138 		dev_err(dev, "aclk_perf clock not found\n");
144 		dev_err(dev, "hclk clock not found\n");
150 		dev_err(dev, "pm clock not found\n");
172 		dev_err(dev, "assert aclk_rst err %d\n", err);
178 		dev_err(dev, "assert pclk_rst err %d\n", err);
184 		dev_err(dev, "assert pm_rst err %d\n", err);
191 			dev_err(dev, "init phy%d err %d\n", i, err);
198 		dev_err(dev, "assert core_rst err %d\n", err);
204 		dev_err(dev, "assert mgmt_rst err %d\n", err);
210 		dev_err(dev, "assert mgmt_sticky_rst err %d\n", err);
216 		dev_err(dev, "assert pipe_rst err %d\n", err);
224 		dev_err(dev, "deassert pm_rst err %d\n", err);
230 		dev_err(dev, "deassert aclk_rst err %d\n", err);
236 		dev_err(dev, "deassert pclk_rst err %d\n", err);
260 			dev_err(dev, "power on phy%d err %d\n", i, err);
271 		dev_err(dev, "PHY PLLs could not lock, %d\n", err);
281 		dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
287 		dev_err(dev, "deassert core_rst err %d\n", err);
293 		dev_err(dev, "deassert mgmt_rst err %d\n", err);
299 		dev_err(dev, "deassert pipe_rst err %d\n", err);
345 				dev_err(dev, "missing phy for lane %d: %ld\n",
377 		dev_err(dev, "unable to enable aclk_pcie clock\n");
383 		dev_err(dev, "unable to enable aclk_perf_pcie clock\n");
389 		dev_err(dev, "unable to enable hclk_pcie clock\n");
395 		dev_err(dev, "unable to enable clk_pcie_pm clock\n");