Lines Matching refs:pcie
187 #define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX])
188 #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA])
189 #define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1])
227 void (*perst_set)(struct brcm_pcie *pcie, u32 val);
228 void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
271 void (*perst_set)(struct brcm_pcie *pcie, u32 val);
272 void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
277 static inline bool is_bmips(const struct brcm_pcie *pcie)
279 return pcie->type == BCM7435 || pcie->type == BCM7425;
348 static int brcm_pcie_set_ssc(struct brcm_pcie *pcie)
354 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET,
359 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0,
366 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0,
372 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0,
384 static void brcm_pcie_set_gen(struct brcm_pcie *pcie, int gen)
386 u16 lnkctl2 = readw(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
387 u32 lnkcap = readl(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
390 writel(lnkcap, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
393 writew(lnkctl2, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
396 static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
406 writel(lower_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_LO(win));
407 writel(upper_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_HI(win));
413 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win));
418 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win));
420 if (is_bmips(pcie))
428 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_HI(win));
431 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_HI(win));
434 tmp = readl(pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win));
437 writel(tmp, pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win));
590 static void brcm_msi_remove(struct brcm_pcie *pcie)
592 struct brcm_msi *msi = pcie->msi;
621 static int brcm_pcie_enable_msi(struct brcm_pcie *pcie)
625 struct device *dev = pcie->dev;
639 msi->base = pcie->base;
640 msi->np = pcie->np;
641 msi->target_addr = pcie->msi_target_addr;
643 msi->legacy = pcie->hw_rev < BRCM_PCIE_HW_REV_33;
668 pcie->msi = msi;
674 static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie)
676 void __iomem *base = pcie->base;
682 static bool brcm_pcie_link_up(struct brcm_pcie *pcie)
684 u32 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS);
694 struct brcm_pcie *pcie = bus->sysdata;
695 void __iomem *base = pcie->base;
703 if (!brcm_pcie_link_up(pcie))
708 writel(idx, pcie->base + PCIE_EXT_CFG_INDEX);
715 struct brcm_pcie *pcie = bus->sysdata;
716 void __iomem *base = pcie->base;
724 if (!brcm_pcie_link_up(pcie))
729 writel(idx, base + IDX_ADDR(pcie));
730 return base + DATA_ADDR(pcie);
733 static void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val)
738 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
740 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
743 static void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val)
748 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
750 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
753 static void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val)
755 if (WARN_ONCE(!pcie->perst_reset, "missing PERST# reset controller\n"))
759 reset_control_assert(pcie->perst_reset);
761 reset_control_deassert(pcie->perst_reset);
764 static void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val)
769 tmp = readl(pcie->base + PCIE_MISC_PCIE_CTRL);
771 writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL);
774 static void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val)
778 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
780 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
783 static int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie,
787 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
789 struct device *dev = pcie->dev;
807 ret = of_property_read_variable_u64_array(pcie->np, "brcm,scb-sizes", pcie->memc_size, 1,
812 pcie->num_memc = 1;
813 pcie->memc_size[0] = 1ULL << fls64(size - 1);
815 pcie->num_memc = ret;
819 for (i = 0, size = 0; i < pcie->num_memc; i++)
820 size += pcie->memc_size[i];
840 * matters, the viewport must start on a pcie-address that is aligned
851 * region in the first 4GB of pcie-space, as some legacy devices can
870 static int brcm_pcie_setup(struct brcm_pcie *pcie)
873 void __iomem *base = pcie->base;
881 pcie->bridge_sw_init_set(pcie, 1);
884 if (pcie->type == BCM2711)
885 pcie->perst_set(pcie, 1);
890 pcie->bridge_sw_init_set(pcie, 0);
893 if (is_bmips(pcie))
906 if (is_bmips(pcie))
908 else if (pcie->type == BCM2711)
910 else if (pcie->type == BCM7278)
927 ret = brcm_pcie_get_rc_bar2_size_and_offset(pcie, &rc_bar2_size,
940 for (memc = 0; memc < pcie->num_memc; memc++) {
941 u32 scb_size_val = ilog2(pcie->memc_size[memc]) - 15;
960 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_LT_4GB;
962 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_GT_4GB;
964 if (!brcm_pcie_rc_mode(pcie)) {
965 dev_err(pcie->dev, "PCIe RC controller misconfigured as Endpoint\n");
981 if (!of_property_read_bool(pcie->np, "aspm-no-l0s"))
997 bridge = pci_host_bridge_from_priv(pcie);
1005 dev_err(pcie->dev, "too many outbound wins\n");
1009 if (is_bmips(pcie)) {
1017 brcm_pcie_set_outbound_win(pcie, j, start,
1022 brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start,
1042 static void brcm_extend_rbus_timeout(struct brcm_pcie *pcie)
1045 const unsigned int REG_OFFSET = PCIE_RGR1_SW_INIT_1(pcie) - 8;
1049 writel(216 * timeout_us, pcie->base + REG_OFFSET);
1052 static void brcm_config_clkreq(struct brcm_pcie *pcie)
1059 ret = of_property_read_string(pcie->np, "brcm,clkreq-mode", &mode);
1061 dev_err(pcie->dev, err_msg);
1066 clkreq_cntl = readl(pcie->base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
1084 tmp = readl(pcie->base + PCIE_RC_CFG_PRIV1_ROOT_CAP);
1086 writel(tmp, pcie->base + PCIE_RC_CFG_PRIV1_ROOT_CAP);
1098 brcm_extend_rbus_timeout(pcie);
1106 dev_err(pcie->dev, err_msg);
1109 writel(clkreq_cntl, pcie->base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
1111 dev_info(pcie->dev, "clkreq-mode set to %s\n", mode);
1114 static int brcm_pcie_start_link(struct brcm_pcie *pcie)
1116 struct device *dev = pcie->dev;
1117 void __iomem *base = pcie->base;
1123 pcie->perst_set(pcie, 0);
1136 for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5)
1139 if (!brcm_pcie_link_up(pcie)) {
1144 brcm_config_clkreq(pcie);
1146 if (pcie->gen)
1147 brcm_pcie_set_gen(pcie, pcie->gen);
1149 if (pcie->ssc) {
1150 ret = brcm_pcie_set_ssc(pcie);
1192 struct brcm_pcie *pcie = bus->sysdata;
1207 pcie->sr = sr;
1219 pcie->sr = NULL;
1224 brcm_pcie_start_link(pcie);
1230 struct brcm_pcie *pcie = bus->sysdata;
1231 struct subdev_regulators *sr = pcie->sr;
1240 pcie->sr = NULL;
1244 static void brcm_pcie_enter_l23(struct brcm_pcie *pcie)
1246 void __iomem *base = pcie->base;
1266 dev_err(pcie->dev, "failed to enter low-power link state\n");
1269 static int brcm_phy_cntl(struct brcm_pcie *pcie, const int start)
1283 void __iomem *base = pcie->base;
1300 dev_err(pcie->dev, "failed to %s phy\n", (start ? "start" : "stop"));
1305 static inline int brcm_phy_start(struct brcm_pcie *pcie)
1307 return pcie->rescal ? brcm_phy_cntl(pcie, 1) : 0;
1310 static inline int brcm_phy_stop(struct brcm_pcie *pcie)
1312 return pcie->rescal ? brcm_phy_cntl(pcie, 0) : 0;
1315 static void brcm_pcie_turn_off(struct brcm_pcie *pcie)
1317 void __iomem *base = pcie->base;
1320 if (brcm_pcie_link_up(pcie))
1321 brcm_pcie_enter_l23(pcie);
1323 pcie->perst_set(pcie, 1);
1336 pcie->bridge_sw_init_set(pcie, 1);
1352 struct brcm_pcie *pcie = dev_get_drvdata(dev);
1353 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
1356 brcm_pcie_turn_off(pcie);
1362 if (brcm_phy_stop(pcie))
1365 ret = reset_control_rearm(pcie->rescal);
1371 if (pcie->sr) {
1377 pcie->ep_wakeup_capable = false;
1379 &pcie->ep_wakeup_capable);
1380 if (!pcie->ep_wakeup_capable) {
1381 ret = regulator_bulk_disable(pcie->sr->num_supplies,
1382 pcie->sr->supplies);
1385 reset_control_reset(pcie->rescal);
1390 clk_disable_unprepare(pcie->clk);
1397 struct brcm_pcie *pcie = dev_get_drvdata(dev);
1402 base = pcie->base;
1403 ret = clk_prepare_enable(pcie->clk);
1407 ret = reset_control_reset(pcie->rescal);
1411 ret = brcm_phy_start(pcie);
1416 pcie->bridge_sw_init_set(pcie, 0);
1426 ret = brcm_pcie_setup(pcie);
1430 if (pcie->sr) {
1431 if (pcie->ep_wakeup_capable) {
1438 pcie->ep_wakeup_capable = false;
1440 ret = regulator_bulk_enable(pcie->sr->num_supplies,
1441 pcie->sr->supplies);
1449 ret = brcm_pcie_start_link(pcie);
1453 if (pcie->msi)
1454 brcm_msi_set_regs(pcie->msi);
1459 if (pcie->sr)
1460 regulator_bulk_disable(pcie->sr->num_supplies, pcie->sr->supplies);
1462 reset_control_rearm(pcie->rescal);
1464 clk_disable_unprepare(pcie->clk);
1468 static void __brcm_pcie_remove(struct brcm_pcie *pcie)
1470 brcm_msi_remove(pcie);
1471 brcm_pcie_turn_off(pcie);
1472 if (brcm_phy_stop(pcie))
1473 dev_err(pcie->dev, "Could not stop phy\n");
1474 if (reset_control_rearm(pcie->rescal))
1475 dev_err(pcie->dev, "Could not rearm rescal reset\n");
1476 clk_disable_unprepare(pcie->clk);
1481 struct brcm_pcie *pcie = platform_get_drvdata(pdev);
1482 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
1486 __brcm_pcie_remove(pcie);
1550 { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
1551 { .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg },
1552 { .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg },
1553 { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
1554 { .compatible = "brcm,bcm7216-pcie", .data = &bcm7278_cfg },
1555 { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
1556 { .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg },
1557 { .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg },
1582 struct brcm_pcie *pcie;
1585 bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie));
1595 pcie = pci_host_bridge_priv(bridge);
1596 pcie->dev = &pdev->dev;
1597 pcie->np = np;
1598 pcie->reg_offsets = data->offsets;
1599 pcie->type = data->type;
1600 pcie->perst_set = data->perst_set;
1601 pcie->bridge_sw_init_set = data->bridge_sw_init_set;
1603 pcie->base = devm_platform_ioremap_resource(pdev, 0);
1604 if (IS_ERR(pcie->base))
1605 return PTR_ERR(pcie->base);
1607 pcie->clk = devm_clk_get_optional(&pdev->dev, "sw_pcie");
1608 if (IS_ERR(pcie->clk))
1609 return PTR_ERR(pcie->clk);
1612 pcie->gen = (ret < 0) ? 0 : ret;
1614 pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc");
1616 ret = clk_prepare_enable(pcie->clk);
1621 pcie->rescal = devm_reset_control_get_optional_shared(&pdev->dev, "rescal");
1622 if (IS_ERR(pcie->rescal)) {
1623 clk_disable_unprepare(pcie->clk);
1624 return PTR_ERR(pcie->rescal);
1626 pcie->perst_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "perst");
1627 if (IS_ERR(pcie->perst_reset)) {
1628 clk_disable_unprepare(pcie->clk);
1629 return PTR_ERR(pcie->perst_reset);
1632 ret = reset_control_reset(pcie->rescal);
1636 ret = brcm_phy_start(pcie);
1638 reset_control_rearm(pcie->rescal);
1639 clk_disable_unprepare(pcie->clk);
1643 ret = brcm_pcie_setup(pcie);
1647 pcie->hw_rev = readl(pcie->base + PCIE_MISC_REVISION);
1648 if (pcie->type == BCM4908 && pcie->hw_rev >= BRCM_PCIE_HW_REV_3_20) {
1649 dev_err(pcie->dev, "hardware revision with unsupported PERST# setup\n");
1654 msi_np = of_parse_phandle(pcie->np, "msi-parent", 0);
1655 if (pci_msi_enabled() && msi_np == pcie->np) {
1656 ret = brcm_pcie_enable_msi(pcie);
1658 dev_err(pcie->dev, "probe of internal MSI failed");
1663 bridge->ops = pcie->type == BCM7425 ? &brcm7425_pcie_ops : &brcm_pcie_ops;
1664 bridge->sysdata = pcie;
1666 platform_set_drvdata(pdev, pcie);
1669 if (!ret && !brcm_pcie_link_up(pcie))
1680 __brcm_pcie_remove(pcie);
1695 .name = "brcm-pcie",