pci/controller/pci-tegra.c

43 #include <soc/tegra/cpuidle.h>
44 #include <soc/tegra/pmc.h>
352 	const struct tegra_pcie_soc *soc;
487 	const struct tegra_pcie_soc *soc = port->pcie->soc;
500 		ret = soc->afi_pex2_ctrl;
534 	const struct tegra_pcie_soc *soc = port->pcie->soc;
560 	if (soc->update_clamp_threshold) {
572 	const struct tegra_pcie_soc *soc = port->pcie->soc;
577 	value |= soc->ectl.regs.rp_ectl_2_r1;
582 	value |= soc->ectl.regs.rp_ectl_4_r1 <<
588 	value |= soc->ectl.regs.rp_ectl_5_r1;
593 	value |= soc->ectl.regs.rp_ectl_6_r1;
598 	value |= soc->ectl.regs.rp_ectl_2_r2;
603 	value |= soc->ectl.regs.rp_ectl_4_r2 <<
609 	value |= soc->ectl.regs.rp_ectl_5_r2;
614 	value |= soc->ectl.regs.rp_ectl_6_r2;
620 	const struct tegra_pcie_soc *soc = port->pcie->soc;
628 	if (soc->program_deskew_time) {
635 	if (soc->update_fc_timer) {
638 		value |= soc->update_fc_threshold;
657 	const struct tegra_pcie_soc *soc = port->pcie->soc;
664 	if (soc->has_pex_clkreq_en)
673 	if (soc->force_pca_enable) {
681 	if (soc->ectl.enable)
690 	const struct tegra_pcie_soc *soc = port->pcie->soc;
701 	if (soc->has_pex_clkreq_en)
879 	if (pcie->soc->has_cache_bars) {
896 	const struct tegra_pcie_soc *soc = pcie->soc;
902 		value = pads_readl(pcie, soc->pads_pll_ctl);
913 	const struct tegra_pcie_soc *soc = pcie->soc;
929 	value = pads_readl(pcie, soc->pads_pll_ctl);
931 	value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel;
932 	pads_writel(pcie, value, soc->pads_pll_ctl);
935 	value = pads_readl(pcie, soc->pads_pll_ctl);
937 	pads_writel(pcie, value, soc->pads_pll_ctl);
942 	value = pads_readl(pcie, soc->pads_pll_ctl);
944 	pads_writel(pcie, value, soc->pads_pll_ctl);
968 	const struct tegra_pcie_soc *soc = pcie->soc;
982 	value = pads_readl(pcie, soc->pads_pll_ctl);
984 	pads_writel(pcie, value, soc->pads_pll_ctl);
1090 	const struct tegra_pcie_soc *soc = pcie->soc;
1103 	if (soc->has_pex_bias_ctrl)
1119 	if (soc->has_gen2) {
1139 	if (soc->has_intr_prsnt_sense)
1155 	const struct tegra_pcie_soc *soc = pcie->soc;
1161 	if (soc->has_cml_clk)
1176 	const struct tegra_pcie_soc *soc = pcie->soc;
1210 	if (soc->has_cml_clk) {
1229 	if (soc->has_cml_clk)
1244 	const struct tegra_pcie_soc *soc = pcie->soc;
1247 	pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0);
1249 	if (soc->num_ports > 2)
1250 		pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1);
1256 	const struct tegra_pcie_soc *soc = pcie->soc;
1270 	if (soc->has_cml_clk) {
1373 	const struct tegra_pcie_soc *soc = pcie->soc;
1378 	if (!soc->has_gen2 || of_property_present(np, "phys"))
1418 	const struct tegra_pcie_soc *soc = pcie->soc;
1433 	if (soc->program_uphy) {
1487 	if (soc->program_uphy)
1495 	const struct tegra_pcie_soc *soc = pcie->soc;
1500 	if (soc->program_uphy)
1509 	const struct tegra_pcie_soc *soc = pcie->soc;
1515 	val |= (0x1 << soc->ports[port->index].pme.turnoff_bit);
1518 	ack_bit = soc->ports[port->index].pme.ack_bit;
1528 	val &= ~(0x1 << soc->ports[port->index].pme.turnoff_bit);
1793 	const struct tegra_pcie_soc *soc = pcie->soc;
1798 	afi_writel(pcie, msi->phys >> soc->msi_base_shift, AFI_MSI_FPCI_BAR_ST);
2116 	const struct tegra_pcie_soc *soc = pcie->soc;
2136 		if (index < 1 || index > soc->num_ports) {
2374 	if (pcie->soc->has_gen2)
2633 	pcie->soc = of_device_get_match_data(dev);
2723 	if (pcie->soc->program_uphy) {
2772 	if (pcie->soc->program_uphy) {