Lines Matching refs:pcie
293 static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg)
295 writel(val, pcie->base + reg);
298 static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg)
300 return readl(pcie->base + reg);
303 static u8 advk_pcie_ltssm_state(struct advk_pcie *pcie)
308 val = advk_readl(pcie, CFG_REG);
313 static inline bool advk_pcie_link_up(struct advk_pcie *pcie)
316 u8 ltssm_state = advk_pcie_ltssm_state(pcie);
320 static inline bool advk_pcie_link_active(struct advk_pcie *pcie)
330 u8 ltssm_state = advk_pcie_ltssm_state(pcie);
334 static inline bool advk_pcie_link_training(struct advk_pcie *pcie)
341 u8 ltssm_state = advk_pcie_ltssm_state(pcie);
348 static int advk_pcie_wait_for_link(struct advk_pcie *pcie)
354 if (advk_pcie_link_up(pcie))
363 static void advk_pcie_wait_for_retrain(struct advk_pcie *pcie)
368 if (advk_pcie_link_training(pcie))
374 static void advk_pcie_issue_perst(struct advk_pcie *pcie)
376 if (!pcie->reset_gpio)
380 dev_info(&pcie->pdev->dev, "issuing PERST via reset GPIO for 10ms\n");
381 gpiod_set_value_cansleep(pcie->reset_gpio, 1);
383 gpiod_set_value_cansleep(pcie->reset_gpio, 0);
386 static void advk_pcie_train_link(struct advk_pcie *pcie)
388 struct device *dev = &pcie->pdev->dev;
396 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
398 if (pcie->link_gen == 3)
400 else if (pcie->link_gen == 2)
404 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
411 reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL2);
413 if (pcie->link_gen == 3)
415 else if (pcie->link_gen == 2)
419 advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL2);
422 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
424 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
430 advk_pcie_issue_perst(pcie);
443 ret = advk_pcie_wait_for_link(pcie);
454 static void advk_pcie_set_ob_win(struct advk_pcie *pcie, u8 win_num,
458 advk_writel(pcie, OB_WIN_ENABLE |
460 advk_writel(pcie, upper_32_bits(match), OB_WIN_MATCH_MS(win_num));
461 advk_writel(pcie, lower_32_bits(remap), OB_WIN_REMAP_LS(win_num));
462 advk_writel(pcie, upper_32_bits(remap), OB_WIN_REMAP_MS(win_num));
463 advk_writel(pcie, lower_32_bits(mask), OB_WIN_MASK_LS(win_num));
464 advk_writel(pcie, upper_32_bits(mask), OB_WIN_MASK_MS(win_num));
465 advk_writel(pcie, actions, OB_WIN_ACTIONS(win_num));
468 static void advk_pcie_disable_ob_win(struct advk_pcie *pcie, u8 win_num)
470 advk_writel(pcie, 0, OB_WIN_MATCH_LS(win_num));
471 advk_writel(pcie, 0, OB_WIN_MATCH_MS(win_num));
472 advk_writel(pcie, 0, OB_WIN_REMAP_LS(win_num));
473 advk_writel(pcie, 0, OB_WIN_REMAP_MS(win_num));
474 advk_writel(pcie, 0, OB_WIN_MASK_LS(win_num));
475 advk_writel(pcie, 0, OB_WIN_MASK_MS(win_num));
476 advk_writel(pcie, 0, OB_WIN_ACTIONS(win_num));
479 static void advk_pcie_setup_hw(struct advk_pcie *pcie)
491 reg = advk_readl(pcie, PCIE_CORE_REF_CLK_REG);
494 advk_writel(pcie, reg, PCIE_CORE_REF_CLK_REG);
497 reg = advk_readl(pcie, CTRL_CONFIG_REG);
500 advk_writel(pcie, reg, CTRL_CONFIG_REG);
503 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
505 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
515 advk_writel(pcie, reg, VENDOR_ID_REG);
532 reg = advk_readl(pcie, PCIE_CORE_DEV_REV_REG);
535 advk_writel(pcie, reg, PCIE_CORE_DEV_REV_REG);
538 reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
540 advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
547 advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG);
550 reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL);
557 advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL);
562 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
565 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
568 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
571 msi_addr = virt_to_phys(pcie);
572 advk_writel(pcie, lower_32_bits(msi_addr), PCIE_MSI_ADDR_LOW_REG);
573 advk_writel(pcie, upper_32_bits(msi_addr), PCIE_MSI_ADDR_HIGH_REG);
576 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
578 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
581 advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_STATUS_REG);
582 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG);
583 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);
584 advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);
587 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_MASK_REG);
588 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);
589 advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG);
592 reg = advk_readl(pcie, PCIE_ISR0_MASK_REG);
594 advk_writel(pcie, reg, PCIE_ISR0_MASK_REG);
597 reg = advk_readl(pcie, PCIE_ISR0_MASK_REG);
599 advk_writel(pcie, reg, PCIE_ISR0_MASK_REG);
603 advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG);
615 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
617 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
624 advk_writel(pcie, OB_WIN_TYPE_MEM, OB_WIN_DEFAULT_ACTIONS);
632 reg = advk_readl(pcie, PIO_CTRL);
634 advk_writel(pcie, reg, PIO_CTRL);
641 for (i = 0; i < pcie->wins_count; i++)
642 advk_pcie_set_ob_win(pcie, i,
643 pcie->wins[i].match, pcie->wins[i].remap,
644 pcie->wins[i].mask, pcie->wins[i].actions);
647 for (i = pcie->wins_count; i < OB_WIN_COUNT; i++)
648 advk_pcie_disable_ob_win(pcie, i);
650 advk_pcie_train_link(pcie);
653 static int advk_pcie_check_pio_status(struct advk_pcie *pcie, bool allow_crs, u32 *val)
655 struct device *dev = &pcie->pdev->dev;
661 reg = advk_readl(pcie, PIO_STAT);
689 *val = advk_readl(pcie, PIO_RD_DATA);
755 str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS));
760 static int advk_pcie_wait_pio(struct advk_pcie *pcie)
762 struct device *dev = &pcie->pdev->dev;
768 start = advk_readl(pcie, PIO_START);
769 isr = advk_readl(pcie, PIO_ISR);
783 struct advk_pcie *pcie = bridge->data;
787 *value = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
798 if (advk_readl(pcie, PCIE_ISR0_MASK_REG) & PCIE_ISR0_ERR_MASK)
802 if (advk_readl(pcie, PCIE_CORE_CTRL1_REG) & HOT_RESET_GEN)
819 struct advk_pcie *pcie = bridge->data;
823 advk_writel(pcie, new, PCIE_CORE_CMD_STATUS_REG);
833 u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG);
838 advk_writel(pcie, val, PCIE_ISR0_MASK_REG);
841 u32 val = advk_readl(pcie, PCIE_CORE_CTRL1_REG);
846 advk_writel(pcie, val, PCIE_CORE_CTRL1_REG);
859 struct advk_pcie *pcie = bridge->data;
871 u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg);
884 u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg) &
886 if (advk_pcie_link_training(pcie))
888 if (advk_pcie_link_active(pcie))
900 *value = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg);
913 struct advk_pcie *pcie = bridge->data;
917 advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg);
919 advk_pcie_wait_for_retrain(pcie);
939 advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg);
951 struct advk_pcie *pcie = bridge->data;
955 *value = advk_readl(pcie, PCIE_CORE_PCIERR_CAP + reg);
983 *value = advk_readl(pcie, PCIE_CORE_PCIERR_CAP + reg);
995 struct advk_pcie *pcie = bridge->data;
1015 advk_writel(pcie, new, PCIE_CORE_PCIERR_CAP + reg);
1036 static int advk_sw_pci_bridge_init(struct advk_pcie *pcie)
1038 struct pci_bridge_emul *bridge = &pcie->bridge;
1041 cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff);
1043 cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16);
1045 cpu_to_le32(advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff);
1081 bridge->subsystem_vendor_id = advk_readl(pcie, PCIE_CORE_SSDEV_ID_REG) & 0xffff;
1082 bridge->subsystem_id = advk_readl(pcie, PCIE_CORE_SSDEV_ID_REG) >> 16;
1085 bridge->data = pcie;
1091 static bool advk_pcie_valid_device(struct advk_pcie *pcie, struct pci_bus *bus,
1105 if (!pci_is_root_bus(bus) && !advk_pcie_link_up(pcie))
1111 static bool advk_pcie_pio_is_running(struct advk_pcie *pcie)
1113 struct device *dev = &pcie->pdev->dev;
1132 if (advk_readl(pcie, PIO_START)) {
1143 struct advk_pcie *pcie = bus->sysdata;
1149 if (!advk_pcie_valid_device(pcie, bus, devfn))
1153 return pci_bridge_emul_conf_read(&pcie->bridge, where,
1162 (le16_to_cpu(pcie->bridge.pcie_conf.rootctl) &
1165 if (advk_pcie_pio_is_running(pcie))
1169 reg = advk_readl(pcie, PIO_CTRL);
1175 advk_writel(pcie, reg, PIO_CTRL);
1179 advk_writel(pcie, reg, PIO_ADDR_LS);
1180 advk_writel(pcie, 0, PIO_ADDR_MS);
1183 advk_writel(pcie, 0xf, PIO_WR_DATA_STRB);
1188 advk_writel(pcie, 1, PIO_ISR);
1189 advk_writel(pcie, 1, PIO_START);
1191 ret = advk_pcie_wait_pio(pcie);
1198 ret = advk_pcie_check_pio_status(pcie, allow_crs, val);
1229 struct advk_pcie *pcie = bus->sysdata;
1236 if (!advk_pcie_valid_device(pcie, bus, devfn))
1240 return pci_bridge_emul_conf_write(&pcie->bridge, where,
1246 if (advk_pcie_pio_is_running(pcie))
1250 reg = advk_readl(pcie, PIO_CTRL);
1256 advk_writel(pcie, reg, PIO_CTRL);
1260 advk_writel(pcie, reg, PIO_ADDR_LS);
1261 advk_writel(pcie, 0, PIO_ADDR_MS);
1269 advk_writel(pcie, reg, PIO_WR_DATA);
1272 advk_writel(pcie, data_strobe, PIO_WR_DATA_STRB);
1277 advk_writel(pcie, 1, PIO_ISR);
1278 advk_writel(pcie, 1, PIO_START);
1280 ret = advk_pcie_wait_pio(pcie);
1286 ret = advk_pcie_check_pio_status(pcie, false, NULL);
1300 struct advk_pcie *pcie = irq_data_get_irq_chip_data(data);
1301 phys_addr_t msi_addr = virt_to_phys(pcie);
1316 struct advk_pcie *pcie = d->domain->host_data;
1321 raw_spin_lock_irqsave(&pcie->msi_irq_lock, flags);
1322 mask = advk_readl(pcie, PCIE_MSI_MASK_REG);
1324 advk_writel(pcie, mask, PCIE_MSI_MASK_REG);
1325 raw_spin_unlock_irqrestore(&pcie->msi_irq_lock, flags);
1330 struct advk_pcie *pcie = d->domain->host_data;
1335 raw_spin_lock_irqsave(&pcie->msi_irq_lock, flags);
1336 mask = advk_readl(pcie, PCIE_MSI_MASK_REG);
1338 advk_writel(pcie, mask, PCIE_MSI_MASK_REG);
1339 raw_spin_unlock_irqrestore(&pcie->msi_irq_lock, flags);
1366 struct advk_pcie *pcie = domain->host_data;
1369 mutex_lock(&pcie->msi_used_lock);
1370 hwirq = bitmap_find_free_region(pcie->msi_used, MSI_IRQ_NUM,
1372 mutex_unlock(&pcie->msi_used_lock);
1389 struct advk_pcie *pcie = domain->host_data;
1391 mutex_lock(&pcie->msi_used_lock);
1392 bitmap_release_region(pcie->msi_used, d->hwirq, order_base_2(nr_irqs));
1393 mutex_unlock(&pcie->msi_used_lock);
1403 struct advk_pcie *pcie = d->domain->host_data;
1408 raw_spin_lock_irqsave(&pcie->irq_lock, flags);
1409 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
1411 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
1412 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags);
1417 struct advk_pcie *pcie = d->domain->host_data;
1422 raw_spin_lock_irqsave(&pcie->irq_lock, flags);
1423 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
1425 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
1426 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags);
1432 struct advk_pcie *pcie = h->host_data;
1435 irq_set_chip_and_handler(virq, &pcie->irq_chip,
1437 irq_set_chip_data(virq, pcie);
1459 static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie)
1461 struct device *dev = &pcie->pdev->dev;
1463 raw_spin_lock_init(&pcie->msi_irq_lock);
1464 mutex_init(&pcie->msi_used_lock);
1466 pcie->msi_inner_domain =
1468 &advk_msi_domain_ops, pcie);
1469 if (!pcie->msi_inner_domain)
1472 pcie->msi_domain =
1475 pcie->msi_inner_domain);
1476 if (!pcie->msi_domain) {
1477 irq_domain_remove(pcie->msi_inner_domain);
1484 static void advk_pcie_remove_msi_irq_domain(struct advk_pcie *pcie)
1486 irq_domain_remove(pcie->msi_domain);
1487 irq_domain_remove(pcie->msi_inner_domain);
1490 static int advk_pcie_init_irq_domain(struct advk_pcie *pcie)
1492 struct device *dev = &pcie->pdev->dev;
1498 raw_spin_lock_init(&pcie->irq_lock);
1506 irq_chip = &pcie->irq_chip;
1518 pcie->irq_domain =
1520 &advk_pcie_irq_domain_ops, pcie);
1521 if (!pcie->irq_domain) {
1532 static void advk_pcie_remove_irq_domain(struct advk_pcie *pcie)
1534 irq_domain_remove(pcie->irq_domain);
1544 struct advk_pcie *pcie = h->host_data;
1547 irq_set_chip_data(virq, pcie);
1557 static int advk_pcie_init_rp_irq_domain(struct advk_pcie *pcie)
1559 pcie->rp_irq_domain = irq_domain_add_linear(NULL, 1,
1561 pcie);
1562 if (!pcie->rp_irq_domain) {
1563 dev_err(&pcie->pdev->dev, "Failed to add Root Port IRQ domain\n");
1570 static void advk_pcie_remove_rp_irq_domain(struct advk_pcie *pcie)
1572 irq_domain_remove(pcie->rp_irq_domain);
1575 static void advk_pcie_handle_pme(struct advk_pcie *pcie)
1577 u32 requester = advk_readl(pcie, PCIE_MSG_LOG_REG) >> 16;
1579 advk_writel(pcie, PCIE_MSG_PM_PME_MASK, PCIE_ISR0_REG);
1586 if (!(le32_to_cpu(pcie->bridge.pcie_conf.rootsta) & PCI_EXP_RTSTA_PME)) {
1587 pcie->bridge.pcie_conf.rootsta = cpu_to_le32(requester | PCI_EXP_RTSTA_PME);
1593 if (!(le16_to_cpu(pcie->bridge.pcie_conf.rootctl) & PCI_EXP_RTCTL_PMEIE))
1596 if (generic_handle_domain_irq(pcie->rp_irq_domain, 0) == -EINVAL)
1597 dev_err_ratelimited(&pcie->pdev->dev, "unhandled PME IRQ\n");
1601 static void advk_pcie_handle_msi(struct advk_pcie *pcie)
1605 msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG);
1606 msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG);
1613 advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG);
1614 if (generic_handle_domain_irq(pcie->msi_inner_domain, msi_idx) == -EINVAL)
1615 dev_err_ratelimited(&pcie->pdev->dev, "unexpected MSI 0x%02x\n", msi_idx);
1618 advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING,
1622 static void advk_pcie_handle_int(struct advk_pcie *pcie)
1628 isr0_val = advk_readl(pcie, PCIE_ISR0_REG);
1629 isr0_mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
1632 isr1_val = advk_readl(pcie, PCIE_ISR1_REG);
1633 isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
1638 advk_pcie_handle_pme(pcie);
1642 advk_writel(pcie, PCIE_ISR0_ERR_MASK, PCIE_ISR0_REG);
1648 if (generic_handle_domain_irq(pcie->rp_irq_domain, 0) == -EINVAL)
1649 dev_err_ratelimited(&pcie->pdev->dev, "unhandled ERR IRQ\n");
1654 advk_pcie_handle_msi(pcie);
1661 advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i),
1664 if (generic_handle_domain_irq(pcie->irq_domain, i) == -EINVAL)
1665 dev_err_ratelimited(&pcie->pdev->dev, "unexpected INT%c IRQ\n",
1672 struct advk_pcie *pcie = arg;
1675 status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG);
1679 advk_pcie_handle_int(pcie);
1682 advk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG);
1689 struct advk_pcie *pcie = dev->bus->sysdata;
1697 return irq_create_mapping(pcie->rp_irq_domain, pin - 1);
1702 static void advk_pcie_disable_phy(struct advk_pcie *pcie)
1704 phy_power_off(pcie->phy);
1705 phy_exit(pcie->phy);
1708 static int advk_pcie_enable_phy(struct advk_pcie *pcie)
1712 if (!pcie->phy)
1715 ret = phy_init(pcie->phy);
1719 ret = phy_set_mode(pcie->phy, PHY_MODE_PCIE);
1721 phy_exit(pcie->phy);
1725 ret = phy_power_on(pcie->phy);
1727 phy_exit(pcie->phy);
1734 static int advk_pcie_setup_phy(struct advk_pcie *pcie)
1736 struct device *dev = &pcie->pdev->dev;
1740 pcie->phy = devm_of_phy_get(dev, node, NULL);
1741 if (IS_ERR(pcie->phy) && (PTR_ERR(pcie->phy) == -EPROBE_DEFER))
1742 return PTR_ERR(pcie->phy);
1745 if (IS_ERR(pcie->phy)) {
1746 dev_warn(dev, "PHY unavailable (%ld)\n", PTR_ERR(pcie->phy));
1747 pcie->phy = NULL;
1751 ret = advk_pcie_enable_phy(pcie);
1761 struct advk_pcie *pcie;
1770 pcie = pci_host_bridge_priv(bridge);
1771 pcie->pdev = pdev;
1772 platform_set_drvdata(pdev, pcie);
1806 while (pcie->wins_count < OB_WIN_COUNT && size > 0) {
1816 pcie->wins_count, (unsigned long long)start,
1820 pcie->wins[pcie->wins_count].actions = OB_WIN_TYPE_IO;
1821 pcie->wins[pcie->wins_count].match = pci_pio_to_address(start);
1823 pcie->wins[pcie->wins_count].actions = OB_WIN_TYPE_MEM;
1824 pcie->wins[pcie->wins_count].match = start;
1826 pcie->wins[pcie->wins_count].remap = start - entry->offset;
1827 pcie->wins[pcie->wins_count].mask = ~(win_size - 1);
1829 if (pcie->wins[pcie->wins_count].remap & (win_size - 1))
1834 pcie->wins_count++;
1838 dev_err(&pcie->pdev->dev,
1846 pcie->base = devm_platform_ioremap_resource(pdev, 0);
1847 if (IS_ERR(pcie->base))
1848 return PTR_ERR(pcie->base);
1855 IRQF_SHARED | IRQF_NO_THREAD, "advk-pcie",
1856 pcie);
1862 pcie->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
1863 ret = PTR_ERR_OR_ZERO(pcie->reset_gpio);
1870 ret = gpiod_set_consumer_name(pcie->reset_gpio, "pcie1-reset");
1878 pcie->link_gen = 3;
1880 pcie->link_gen = ret;
1882 ret = advk_pcie_setup_phy(pcie);
1886 advk_pcie_setup_hw(pcie);
1888 ret = advk_sw_pci_bridge_init(pcie);
1894 ret = advk_pcie_init_irq_domain(pcie);
1900 ret = advk_pcie_init_msi_irq_domain(pcie);
1903 advk_pcie_remove_irq_domain(pcie);
1907 ret = advk_pcie_init_rp_irq_domain(pcie);
1910 advk_pcie_remove_msi_irq_domain(pcie);
1911 advk_pcie_remove_irq_domain(pcie);
1915 bridge->sysdata = pcie;
1921 advk_pcie_remove_rp_irq_domain(pcie);
1922 advk_pcie_remove_msi_irq_domain(pcie);
1923 advk_pcie_remove_irq_domain(pcie);
1932 struct advk_pcie *pcie = platform_get_drvdata(pdev);
1933 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
1944 val = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
1946 advk_writel(pcie, val, PCIE_CORE_CMD_STATUS_REG);
1949 val = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
1951 advk_writel(pcie, val, PCIE_CORE_CTRL2_REG);
1954 advk_writel(pcie, 0, PCIE_MSI_ADDR_LOW_REG);
1955 advk_writel(pcie, 0, PCIE_MSI_ADDR_HIGH_REG);
1958 advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG);
1959 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_MASK_REG);
1960 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);
1961 advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_MASK_REG);
1964 advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_STATUS_REG);
1965 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG);
1966 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);
1967 advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);
1970 advk_pcie_remove_rp_irq_domain(pcie);
1971 advk_pcie_remove_msi_irq_domain(pcie);
1972 advk_pcie_remove_irq_domain(pcie);
1975 pci_bridge_emul_cleanup(&pcie->bridge);
1978 if (pcie->reset_gpio)
1979 gpiod_set_value_cansleep(pcie->reset_gpio, 1);
1982 val = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
1984 advk_writel(pcie, val, PCIE_CORE_CTRL0_REG);
1988 advk_pcie_disable_ob_win(pcie, i);
1991 advk_pcie_disable_phy(pcie);
1995 { .compatible = "marvell,armada-3700-pcie", },
2002 .name = "advk-pcie",