controller/dwc/pcie-uniphier.c

23 #include "pcie-designware.h"
75 static void uniphier_pcie_ltssm_enable(struct uniphier_pcie *pcie,
80 	val = readl(pcie->base + PCL_APP_READY_CTRL);
85 	writel(val, pcie->base + PCL_APP_READY_CTRL);
88 static void uniphier_pcie_init_rc(struct uniphier_pcie *pcie)
93 	val = readl(pcie->base + PCL_MODE);
96 	writel(val, pcie->base + PCL_MODE);
99 	val = readl(pcie->base + PCL_APP_PM0);
101 	writel(val, pcie->base + PCL_APP_PM0);
104 	val = readl(pcie->base + PCL_PINCTRL0);
109 	writel(val, pcie->base + PCL_PINCTRL0);
111 	uniphier_pcie_ltssm_enable(pcie, false);
116 	val = readl(pcie->base + PCL_PINCTRL0);
118 	writel(val, pcie->base + PCL_PINCTRL0);
121 static int uniphier_pcie_wait_rc(struct uniphier_pcie *pcie)
127 	ret = readl_poll_timeout(pcie->base + PCL_PIPEMON, status,
130 		dev_err(pcie->pci.dev,
140 	struct uniphier_pcie *pcie = to_uniphier_pcie(pci);
143 	val = readl(pcie->base + PCL_STATUS_LINK);
151 	struct uniphier_pcie *pcie = to_uniphier_pcie(pci);
153 	uniphier_pcie_ltssm_enable(pcie, true);
160 	struct uniphier_pcie *pcie = to_uniphier_pcie(pci);
162 	uniphier_pcie_ltssm_enable(pcie, false);
165 static void uniphier_pcie_irq_enable(struct uniphier_pcie *pcie)
167 	writel(PCL_RCV_INT_ALL_ENABLE, pcie->base + PCL_RCV_INT);
168 	writel(PCL_RCV_INTX_ALL_ENABLE, pcie->base + PCL_RCV_INTX);
176 	struct uniphier_pcie *pcie = to_uniphier_pcie(pci);
182 	val = readl(pcie->base + PCL_RCV_INTX);
184 	writel(val, pcie->base + PCL_RCV_INTX);
193 	struct uniphier_pcie *pcie = to_uniphier_pcie(pci);
199 	val = readl(pcie->base + PCL_RCV_INTX);
201 	writel(val, pcie->base + PCL_RCV_INTX);
230 	struct uniphier_pcie *pcie = to_uniphier_pcie(pci);
236 	val = readl(pcie->base + PCL_RCV_INT);
247 	writel(val, pcie->base + PCL_RCV_INT);
252 	val = readl(pcie->base + PCL_RCV_INTX);
256 		generic_handle_domain_irq(pcie->intx_irq_domain, bit);
264 	struct uniphier_pcie *pcie = to_uniphier_pcie(pci);
282 	pcie->intx_irq_domain = irq_domain_add_linear(np_intc, PCI_NUM_INTX,
284 	if (!pcie->intx_irq_domain) {
301 	struct uniphier_pcie *pcie = to_uniphier_pcie(pci);
308 	uniphier_pcie_irq_enable(pcie);
317 static int uniphier_pcie_host_enable(struct uniphier_pcie *pcie)
321 	ret = clk_prepare_enable(pcie->clk);
325 	ret = reset_control_deassert(pcie->rst);
329 	uniphier_pcie_init_rc(pcie);
331 	ret = phy_init(pcie->phy);
335 	ret = uniphier_pcie_wait_rc(pcie);
342 	phy_exit(pcie->phy);
344 	reset_control_assert(pcie->rst);
346 	clk_disable_unprepare(pcie->clk);
360 	struct uniphier_pcie *pcie;
363 	pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
364 	if (!pcie)
367 	pcie->pci.dev = dev;
368 	pcie->pci.ops = &dw_pcie_ops;
370 	pcie->base = devm_platform_ioremap_resource_byname(pdev, "link");
371 	if (IS_ERR(pcie->base))
372 		return PTR_ERR(pcie->base);
374 	pcie->clk = devm_clk_get(dev, NULL);
375 	if (IS_ERR(pcie->clk))
376 		return PTR_ERR(pcie->clk);
378 	pcie->rst = devm_reset_control_get_shared(dev, NULL);
379 	if (IS_ERR(pcie->rst))
380 		return PTR_ERR(pcie->rst);
382 	pcie->phy = devm_phy_optional_get(dev, "pcie-phy");
383 	if (IS_ERR(pcie->phy))
384 		return PTR_ERR(pcie->phy);
386 	platform_set_drvdata(pdev, pcie);
388 	ret = uniphier_pcie_host_enable(pcie);
392 	pcie->pci.pp.ops = &uniphier_pcie_host_ops;
394 	return dw_pcie_host_init(&pcie->pci.pp);
398 	{ .compatible = "socionext,uniphier-pcie", },
405 		.name = "uniphier-pcie",