Lines Matching refs:pcie
35 #include "pcie-designware.h"
300 static inline void appl_writel(struct tegra_pcie_dw *pcie, const u32 value,
303 writel_relaxed(value, pcie->appl_base + reg);
306 static inline u32 appl_readl(struct tegra_pcie_dw *pcie, const u32 reg)
308 return readl_relaxed(pcie->appl_base + reg);
315 static void tegra_pcie_icc_set(struct tegra_pcie_dw *pcie)
317 struct dw_pcie *pci = &pcie->pci;
320 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA);
327 if (icc_set_bw(pcie->icc_path, Mbps_to_icc(val), 0))
328 dev_err(pcie->dev, "can't set bw[%u]\n", val);
333 clk_set_rate(pcie->core_clk, pcie_gen_freq[speed]);
339 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
348 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA);
351 if (pcie->init_link_width > current_link_width) {
353 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
357 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base +
360 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
363 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base +
371 struct tegra_pcie_dw *pcie = arg;
372 struct dw_pcie *pci = &pcie->pci;
377 status_l0 = appl_readl(pcie, APPL_INTR_STATUS_L0);
379 status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0);
380 appl_writel(pcie, status_l1, APPL_INTR_STATUS_L1_0_0);
381 if (!pcie->of_data->has_sbr_reset_fix &&
384 val = appl_readl(pcie, APPL_CAR_RESET_OVRD);
386 appl_writel(pcie, val, APPL_CAR_RESET_OVRD);
388 val = appl_readl(pcie, APPL_CAR_RESET_OVRD);
390 appl_writel(pcie, val, APPL_CAR_RESET_OVRD);
399 status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_8_0);
401 appl_writel(pcie,
407 val_w = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
410 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base +
413 appl_writel(pcie,
417 val_w = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
425 status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_18);
447 static void pex_ep_event_hot_rst_done(struct tegra_pcie_dw *pcie)
451 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0);
452 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_0_0);
453 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_1);
454 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_2);
455 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_3);
456 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_6);
457 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_7);
458 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_8_0);
459 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_9);
460 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_10);
461 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_11);
462 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_13);
463 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_14);
464 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_15);
465 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_17);
466 appl_writel(pcie, 0xFFFFFFFF, APPL_MSI_CTRL_2);
468 val = appl_readl(pcie, APPL_CTRL);
470 appl_writel(pcie, val, APPL_CTRL);
475 struct tegra_pcie_dw *pcie = arg;
476 struct dw_pcie_ep *ep = &pcie->pci.ep;
477 struct dw_pcie *pci = &pcie->pci;
480 if (test_and_clear_bit(0, &pcie->link_status))
483 tegra_pcie_icc_set(pcie);
485 if (pcie->of_data->has_ltr_req_fix)
489 val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub);
505 appl_writel(pcie, val, APPL_LTR_MSG_1);
508 val = appl_readl(pcie, APPL_LTR_MSG_2);
510 appl_writel(pcie, val, APPL_LTR_MSG_2);
514 val = appl_readl(pcie, APPL_LTR_MSG_2);
522 dev_err(pcie->dev, "Failed to send LTR message\n");
530 struct tegra_pcie_dw *pcie = arg;
534 status_l0 = appl_readl(pcie, APPL_INTR_STATUS_L0);
536 status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0);
537 appl_writel(pcie, status_l1, APPL_INTR_STATUS_L1_0_0);
540 pex_ep_event_hot_rst_done(pcie);
543 link_status = appl_readl(pcie, APPL_LINK_STATUS);
545 dev_dbg(pcie->dev, "Link is up with Host\n");
546 set_bit(0, &pcie->link_status);
555 status_l1 = appl_readl(pcie, APPL_INTR_STATUS_L1_15);
556 appl_writel(pcie, status_l1, APPL_INTR_STATUS_L1_15);
565 dev_warn(pcie->dev, "Random interrupt (STATUS = 0x%08X)\n",
567 appl_writel(pcie, status_l0, APPL_INTR_STATUS_L0);
578 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
586 if (!pcie->of_data->has_msix_doorbell_access_fix &&
600 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
608 if (!pcie->of_data->has_msix_doorbell_access_fix &&
622 static void disable_aspm_l11(struct tegra_pcie_dw *pcie)
626 val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub);
628 dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val);
631 static void disable_aspm_l12(struct tegra_pcie_dw *pcie)
635 val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub);
637 dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val);
640 static inline u32 event_counter_prog(struct tegra_pcie_dw *pcie, u32 event)
644 val = dw_pcie_readl_dbi(&pcie->pci, pcie->ras_des_cap +
650 dw_pcie_writel_dbi(&pcie->pci, pcie->ras_des_cap +
652 val = dw_pcie_readl_dbi(&pcie->pci, pcie->ras_des_cap +
660 struct tegra_pcie_dw *pcie = (struct tegra_pcie_dw *)
665 event_counter_prog(pcie, EVENT_COUNTER_EVENT_Tx_L0S));
668 event_counter_prog(pcie, EVENT_COUNTER_EVENT_Rx_L0S));
671 event_counter_prog(pcie, EVENT_COUNTER_EVENT_L1));
674 event_counter_prog(pcie, EVENT_COUNTER_EVENT_L1_1));
677 event_counter_prog(pcie, EVENT_COUNTER_EVENT_L1_2));
680 dw_pcie_writel_dbi(&pcie->pci, pcie->ras_des_cap +
687 dw_pcie_writel_dbi(&pcie->pci, pcie->ras_des_cap +
693 static void init_host_aspm(struct tegra_pcie_dw *pcie)
695 struct dw_pcie *pci = &pcie->pci;
699 pcie->cfg_link_cap_l1sub = val + PCI_L1SS_CAP;
701 pcie->ras_des_cap = dw_pcie_find_ext_capability(&pcie->pci,
707 dw_pcie_writel_dbi(pci, pcie->ras_des_cap +
711 val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub);
713 val |= (pcie->aspm_cmrt << 8);
714 val |= (pcie->aspm_pwr_on_t << 19);
715 dw_pcie_writel_dbi(pci, pcie->cfg_link_cap_l1sub, val);
720 val |= (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT);
725 static void init_debugfs(struct tegra_pcie_dw *pcie)
727 debugfs_create_devm_seqfile(pcie->dev, "aspm_state_cnt", pcie->debugfs,
731 static inline void disable_aspm_l12(struct tegra_pcie_dw *pcie) { return; }
732 static inline void disable_aspm_l11(struct tegra_pcie_dw *pcie) { return; }
733 static inline void init_host_aspm(struct tegra_pcie_dw *pcie) { return; }
734 static inline void init_debugfs(struct tegra_pcie_dw *pcie) { return; }
740 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
744 val = appl_readl(pcie, APPL_INTR_EN_L0_0);
746 appl_writel(pcie, val, APPL_INTR_EN_L0_0);
748 if (!pcie->of_data->has_sbr_reset_fix) {
749 val = appl_readl(pcie, APPL_INTR_EN_L1_0_0);
751 appl_writel(pcie, val, APPL_INTR_EN_L1_0_0);
754 if (pcie->enable_cdm_check) {
755 val = appl_readl(pcie, APPL_INTR_EN_L0_0);
756 val |= pcie->of_data->cdm_chk_int_en_bit;
757 appl_writel(pcie, val, APPL_INTR_EN_L0_0);
759 val = appl_readl(pcie, APPL_INTR_EN_L1_18);
762 appl_writel(pcie, val, APPL_INTR_EN_L1_18);
765 val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base +
767 pcie->init_link_width = FIELD_GET(PCI_EXP_LNKSTA_NLW, val_w);
769 val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base +
772 dw_pcie_writew_dbi(&pcie->pci, pcie->pcie_cap_base + PCI_EXP_LNKCTL,
779 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
783 val = appl_readl(pcie, APPL_INTR_EN_L0_0);
786 appl_writel(pcie, val, APPL_INTR_EN_L0_0);
788 val = appl_readl(pcie, APPL_INTR_EN_L1_8_0);
794 appl_writel(pcie, val, APPL_INTR_EN_L1_8_0);
800 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
804 val = appl_readl(pcie, APPL_INTR_EN_L0_0);
807 appl_writel(pcie, val, APPL_INTR_EN_L0_0);
813 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
816 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0);
817 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_0_0);
818 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_1);
819 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_2);
820 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_3);
821 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_6);
822 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_7);
823 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_8_0);
824 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_9);
825 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_10);
826 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_11);
827 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_13);
828 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_14);
829 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_15);
830 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_17);
838 static void config_gen3_gen4_eq_presets(struct tegra_pcie_dw *pcie)
840 struct dw_pcie *pci = &pcie->pci;
844 for (i = 0; i < pcie->num_lanes; i++) {
882 val |= (pcie->of_data->gen4_preset_vec <<
895 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
901 if (!pcie->pcie_cap_base)
902 pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci,
924 if (pcie->enable_srns) {
925 val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
928 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA,
932 config_gen3_gen4_eq_presets(pcie);
934 init_host_aspm(pcie);
937 if (!pcie->supports_clkreq) {
938 disable_aspm_l11(pcie);
939 disable_aspm_l12(pcie);
942 if (!pcie->of_data->has_l1ss_exit_fix) {
948 if (pcie->update_fc_fixup) {
954 clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ);
961 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
966 if (pcie->of_data->mode == DW_PCIE_EP_TYPE) {
967 enable_irq(pcie->pex_rst_irq);
973 val = appl_readl(pcie, APPL_PINMUX);
975 appl_writel(pcie, val, APPL_PINMUX);
980 val = appl_readl(pcie, APPL_CTRL);
982 appl_writel(pcie, val, APPL_CTRL);
985 val = appl_readl(pcie, APPL_PINMUX);
987 appl_writel(pcie, val, APPL_PINMUX);
1002 val = appl_readl(pcie, APPL_DEBUG);
1005 tmp = appl_readl(pcie, APPL_LINK_STATUS);
1015 val = appl_readl(pcie, APPL_CTRL);
1017 appl_writel(pcie, val, APPL_CTRL);
1019 reset_control_assert(pcie->core_rst);
1020 reset_control_deassert(pcie->core_rst);
1034 tegra_pcie_icc_set(pcie);
1043 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
1044 u32 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA);
1051 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
1053 disable_irq(pcie->pex_rst_irq);
1066 static void tegra_pcie_disable_phy(struct tegra_pcie_dw *pcie)
1068 unsigned int phy_count = pcie->phy_count;
1071 phy_power_off(pcie->phys[phy_count]);
1072 phy_exit(pcie->phys[phy_count]);
1076 static int tegra_pcie_enable_phy(struct tegra_pcie_dw *pcie)
1081 for (i = 0; i < pcie->phy_count; i++) {
1082 ret = phy_init(pcie->phys[i]);
1086 ret = phy_power_on(pcie->phys[i]);
1095 phy_power_off(pcie->phys[i]);
1097 phy_exit(pcie->phys[i]);
1103 static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie)
1105 struct platform_device *pdev = to_platform_device(pcie->dev);
1106 struct device_node *np = pcie->dev->of_node;
1109 pcie->dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
1110 if (!pcie->dbi_res) {
1111 dev_err(pcie->dev, "Failed to find \"dbi\" region\n");
1115 ret = of_property_read_u32(np, "nvidia,aspm-cmrt-us", &pcie->aspm_cmrt);
1117 dev_info(pcie->dev, "Failed to read ASPM T_cmrt: %d\n", ret);
1122 &pcie->aspm_pwr_on_t);
1124 dev_info(pcie->dev, "Failed to read ASPM Power On time: %d\n",
1128 &pcie->aspm_l0s_enter_lat);
1130 dev_info(pcie->dev,
1133 ret = of_property_read_u32(np, "num-lanes", &pcie->num_lanes);
1135 dev_err(pcie->dev, "Failed to read num-lanes: %d\n", ret);
1139 ret = of_property_read_u32_index(np, "nvidia,bpmp", 1, &pcie->cid);
1141 dev_err(pcie->dev, "Failed to read Controller-ID: %d\n", ret);
1147 dev_err(pcie->dev, "Failed to find PHY entries: %d\n",
1151 pcie->phy_count = ret;
1154 pcie->update_fc_fixup = true;
1157 if (pcie->of_data->version == TEGRA194_DWC_IP_VER) {
1158 if (pcie->of_data->mode == DW_PCIE_EP_TYPE)
1159 pcie->enable_ext_refclk = true;
1161 pcie->enable_ext_refclk =
1162 of_property_read_bool(pcie->dev->of_node,
1166 pcie->supports_clkreq =
1167 of_property_read_bool(pcie->dev->of_node, "supports-clkreq");
1169 pcie->enable_cdm_check =
1172 if (pcie->of_data->version == TEGRA234_DWC_IP_VER)
1173 pcie->enable_srns =
1176 if (pcie->of_data->mode == DW_PCIE_RC_TYPE)
1180 pcie->pex_rst_gpiod = devm_gpiod_get(pcie->dev, "reset", GPIOD_IN);
1181 if (IS_ERR(pcie->pex_rst_gpiod)) {
1182 int err = PTR_ERR(pcie->pex_rst_gpiod);
1188 dev_printk(level, pcie->dev,
1194 pcie->pex_refclk_sel_gpiod = devm_gpiod_get(pcie->dev,
1197 if (IS_ERR(pcie->pex_refclk_sel_gpiod)) {
1198 int err = PTR_ERR(pcie->pex_refclk_sel_gpiod);
1204 dev_printk(level, pcie->dev,
1207 pcie->pex_refclk_sel_gpiod = NULL;
1213 static int tegra_pcie_bpmp_set_ctrl_state(struct tegra_pcie_dw *pcie,
1224 if (pcie->of_data->version == TEGRA194_DWC_IP_VER && pcie->cid == 5)
1231 req.controller_state.pcie_controller = pcie->cid;
1241 return tegra_bpmp_transfer(pcie->bpmp, &msg);
1244 static int tegra_pcie_bpmp_set_pll_state(struct tegra_pcie_dw *pcie,
1256 req.ep_ctrlr_pll_init.ep_controller = pcie->cid;
1259 req.ep_ctrlr_pll_off.ep_controller = pcie->cid;
1269 return tegra_bpmp_transfer(pcie->bpmp, &msg);
1272 static void tegra_pcie_downstream_dev_to_D0(struct tegra_pcie_dw *pcie)
1274 struct dw_pcie_rp *pp = &pcie->pci.pp;
1296 dev_err(pcie->dev, "Failed to find downstream devices\n");
1303 dev_err(pcie->dev,
1310 static int tegra_pcie_get_slot_regulators(struct tegra_pcie_dw *pcie)
1312 pcie->slot_ctl_3v3 = devm_regulator_get_optional(pcie->dev, "vpcie3v3");
1313 if (IS_ERR(pcie->slot_ctl_3v3)) {
1314 if (PTR_ERR(pcie->slot_ctl_3v3) != -ENODEV)
1315 return PTR_ERR(pcie->slot_ctl_3v3);
1317 pcie->slot_ctl_3v3 = NULL;
1320 pcie->slot_ctl_12v = devm_regulator_get_optional(pcie->dev, "vpcie12v");
1321 if (IS_ERR(pcie->slot_ctl_12v)) {
1322 if (PTR_ERR(pcie->slot_ctl_12v) != -ENODEV)
1323 return PTR_ERR(pcie->slot_ctl_12v);
1325 pcie->slot_ctl_12v = NULL;
1331 static int tegra_pcie_enable_slot_regulators(struct tegra_pcie_dw *pcie)
1335 if (pcie->slot_ctl_3v3) {
1336 ret = regulator_enable(pcie->slot_ctl_3v3);
1338 dev_err(pcie->dev,
1344 if (pcie->slot_ctl_12v) {
1345 ret = regulator_enable(pcie->slot_ctl_12v);
1347 dev_err(pcie->dev,
1358 if (pcie->slot_ctl_3v3 || pcie->slot_ctl_12v)
1364 if (pcie->slot_ctl_3v3)
1365 regulator_disable(pcie->slot_ctl_3v3);
1369 static void tegra_pcie_disable_slot_regulators(struct tegra_pcie_dw *pcie)
1371 if (pcie->slot_ctl_12v)
1372 regulator_disable(pcie->slot_ctl_12v);
1373 if (pcie->slot_ctl_3v3)
1374 regulator_disable(pcie->slot_ctl_3v3);
1377 static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie,
1383 ret = tegra_pcie_bpmp_set_ctrl_state(pcie, true);
1385 dev_err(pcie->dev,
1386 "Failed to enable controller %u: %d\n", pcie->cid, ret);
1390 if (pcie->enable_ext_refclk) {
1391 ret = tegra_pcie_bpmp_set_pll_state(pcie, true);
1393 dev_err(pcie->dev, "Failed to init UPHY: %d\n", ret);
1398 ret = tegra_pcie_enable_slot_regulators(pcie);
1402 ret = regulator_enable(pcie->pex_ctl_supply);
1404 dev_err(pcie->dev, "Failed to enable regulator: %d\n", ret);
1408 ret = clk_prepare_enable(pcie->core_clk);
1410 dev_err(pcie->dev, "Failed to enable core clock: %d\n", ret);
1414 ret = reset_control_deassert(pcie->core_apb_rst);
1416 dev_err(pcie->dev, "Failed to deassert core APB reset: %d\n",
1421 if (en_hw_hot_rst || pcie->of_data->has_sbr_reset_fix) {
1423 val = appl_readl(pcie, APPL_CTRL);
1429 appl_writel(pcie, val, APPL_CTRL);
1432 ret = tegra_pcie_enable_phy(pcie);
1434 dev_err(pcie->dev, "Failed to enable PHY: %d\n", ret);
1439 appl_writel(pcie, pcie->dbi_res->start & APPL_CFG_BASE_ADDR_MASK,
1443 appl_writel(pcie, APPL_DM_TYPE_RP, APPL_DM_TYPE);
1445 appl_writel(pcie, 0x0, APPL_CFG_SLCG_OVERRIDE);
1447 val = appl_readl(pcie, APPL_CTRL);
1448 appl_writel(pcie, val | APPL_CTRL_SYS_PRE_DET_STATE, APPL_CTRL);
1450 val = appl_readl(pcie, APPL_CFG_MISC);
1452 appl_writel(pcie, val, APPL_CFG_MISC);
1454 if (pcie->enable_srns || pcie->enable_ext_refclk) {
1461 val = appl_readl(pcie, APPL_PINMUX);
1464 appl_writel(pcie, val, APPL_PINMUX);
1467 if (!pcie->supports_clkreq) {
1468 val = appl_readl(pcie, APPL_PINMUX);
1471 appl_writel(pcie, val, APPL_PINMUX);
1475 appl_writel(pcie,
1476 pcie->atu_dma_res->start & APPL_CFG_IATU_DMA_BASE_ADDR_MASK,
1479 reset_control_deassert(pcie->core_rst);
1484 reset_control_assert(pcie->core_apb_rst);
1486 clk_disable_unprepare(pcie->core_clk);
1488 regulator_disable(pcie->pex_ctl_supply);
1490 tegra_pcie_disable_slot_regulators(pcie);
1492 if (pcie->enable_ext_refclk)
1493 tegra_pcie_bpmp_set_pll_state(pcie, false);
1495 tegra_pcie_bpmp_set_ctrl_state(pcie, false);
1500 static void tegra_pcie_unconfig_controller(struct tegra_pcie_dw *pcie)
1504 ret = reset_control_assert(pcie->core_rst);
1506 dev_err(pcie->dev, "Failed to assert \"core\" reset: %d\n", ret);
1508 tegra_pcie_disable_phy(pcie);
1510 ret = reset_control_assert(pcie->core_apb_rst);
1512 dev_err(pcie->dev, "Failed to assert APB reset: %d\n", ret);
1514 clk_disable_unprepare(pcie->core_clk);
1516 ret = regulator_disable(pcie->pex_ctl_supply);
1518 dev_err(pcie->dev, "Failed to disable regulator: %d\n", ret);
1520 tegra_pcie_disable_slot_regulators(pcie);
1522 if (pcie->enable_ext_refclk) {
1523 ret = tegra_pcie_bpmp_set_pll_state(pcie, false);
1525 dev_err(pcie->dev, "Failed to deinit UPHY: %d\n", ret);
1528 ret = tegra_pcie_bpmp_set_ctrl_state(pcie, false);
1530 dev_err(pcie->dev, "Failed to disable controller %d: %d\n",
1531 pcie->cid, ret);
1534 static int tegra_pcie_init_controller(struct tegra_pcie_dw *pcie)
1536 struct dw_pcie *pci = &pcie->pci;
1540 ret = tegra_pcie_config_controller(pcie, false);
1548 dev_err(pcie->dev, "Failed to add PCIe port: %d\n", ret);
1555 tegra_pcie_unconfig_controller(pcie);
1559 static int tegra_pcie_try_link_l2(struct tegra_pcie_dw *pcie)
1563 if (!tegra_pcie_dw_link_up(&pcie->pci))
1566 val = appl_readl(pcie, APPL_RADM_STATUS);
1568 appl_writel(pcie, val, APPL_RADM_STATUS);
1570 return readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, val,
1575 static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie)
1580 if (!tegra_pcie_dw_link_up(&pcie->pci)) {
1581 dev_dbg(pcie->dev, "PCIe link is not up...!\n");
1593 appl_writel(pcie, 0x0, APPL_INTR_EN_L0_0);
1595 if (tegra_pcie_try_link_l2(pcie)) {
1596 dev_info(pcie->dev, "Link didn't transition to L2 state\n");
1603 data = appl_readl(pcie, APPL_PINMUX);
1605 appl_writel(pcie, data, APPL_PINMUX);
1611 data = readl(pcie->appl_base + APPL_CTRL);
1613 writel(data, pcie->appl_base + APPL_CTRL);
1615 err = readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG,
1623 dev_info(pcie->dev, "Link didn't go to detect state\n");
1629 data = appl_readl(pcie, APPL_PINMUX);
1634 appl_writel(pcie, data, APPL_PINMUX);
1637 static void tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie)
1639 tegra_pcie_downstream_dev_to_D0(pcie);
1640 dw_pcie_host_deinit(&pcie->pci.pp);
1641 tegra_pcie_dw_pme_turnoff(pcie);
1642 tegra_pcie_unconfig_controller(pcie);
1645 static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie)
1647 struct device *dev = pcie->dev;
1666 ret = tegra_pcie_init_controller(pcie);
1672 pcie->link_state = tegra_pcie_dw_link_up(&pcie->pci);
1673 if (!pcie->link_state) {
1684 pcie->debugfs = debugfs_create_dir(name, NULL);
1685 init_debugfs(pcie);
1690 tegra_pcie_deinit_controller(pcie);
1697 static void pex_ep_event_pex_rst_assert(struct tegra_pcie_dw *pcie)
1702 if (pcie->ep_state == EP_STATE_DISABLED)
1706 val = appl_readl(pcie, APPL_CTRL);
1708 appl_writel(pcie, val, APPL_CTRL);
1710 ret = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val,
1716 dev_err(pcie->dev, "Failed to go Detect state: %d\n", ret);
1718 reset_control_assert(pcie->core_rst);
1720 tegra_pcie_disable_phy(pcie);
1722 reset_control_assert(pcie->core_apb_rst);
1724 clk_disable_unprepare(pcie->core_clk);
1726 pm_runtime_put_sync(pcie->dev);
1728 if (pcie->enable_ext_refclk) {
1729 ret = tegra_pcie_bpmp_set_pll_state(pcie, false);
1731 dev_err(pcie->dev, "Failed to turn off UPHY: %d\n",
1735 ret = tegra_pcie_bpmp_set_pll_state(pcie, false);
1737 dev_err(pcie->dev, "Failed to turn off UPHY: %d\n", ret);
1739 pcie->ep_state = EP_STATE_DISABLED;
1740 dev_dbg(pcie->dev, "Uninitialization of endpoint is completed\n");
1743 static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
1745 struct dw_pcie *pci = &pcie->pci;
1747 struct device *dev = pcie->dev;
1752 if (pcie->ep_state == EP_STATE_ENABLED)
1762 ret = tegra_pcie_bpmp_set_ctrl_state(pcie, true);
1764 dev_err(pcie->dev, "Failed to enable controller %u: %d\n",
1765 pcie->cid, ret);
1769 if (pcie->enable_ext_refclk) {
1770 ret = tegra_pcie_bpmp_set_pll_state(pcie, true);
1778 ret = clk_prepare_enable(pcie->core_clk);
1784 ret = reset_control_deassert(pcie->core_apb_rst);
1790 ret = tegra_pcie_enable_phy(pcie);
1797 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0);
1798 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_0_0);
1799 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_1);
1800 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_2);
1801 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_3);
1802 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_6);
1803 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_7);
1804 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_8_0);
1805 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_9);
1806 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_10);
1807 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_11);
1808 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_13);
1809 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_14);
1810 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_15);
1811 appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_17);
1814 val = appl_readl(pcie, APPL_DM_TYPE);
1817 appl_writel(pcie, val, APPL_DM_TYPE);
1819 appl_writel(pcie, 0x0, APPL_CFG_SLCG_OVERRIDE);
1821 val = appl_readl(pcie, APPL_CTRL);
1824 appl_writel(pcie, val, APPL_CTRL);
1826 val = appl_readl(pcie, APPL_CFG_MISC);
1829 appl_writel(pcie, val, APPL_CFG_MISC);
1831 val = appl_readl(pcie, APPL_PINMUX);
1834 appl_writel(pcie, val, APPL_PINMUX);
1836 appl_writel(pcie, pcie->dbi_res->start & APPL_CFG_BASE_ADDR_MASK,
1839 appl_writel(pcie, pcie->atu_dma_res->start &
1843 val = appl_readl(pcie, APPL_INTR_EN_L0_0);
1847 appl_writel(pcie, val, APPL_INTR_EN_L0_0);
1849 val = appl_readl(pcie, APPL_INTR_EN_L1_0_0);
1852 appl_writel(pcie, val, APPL_INTR_EN_L1_0_0);
1854 reset_control_deassert(pcie->core_rst);
1856 if (pcie->update_fc_fixup) {
1862 config_gen3_gen4_eq_presets(pcie);
1864 init_host_aspm(pcie);
1867 if (!pcie->supports_clkreq) {
1868 disable_aspm_l11(pcie);
1869 disable_aspm_l12(pcie);
1872 if (!pcie->of_data->has_l1ss_exit_fix) {
1878 pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci,
1882 if (pcie->enable_srns) {
1883 val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
1886 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA,
1890 clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ);
1907 if (pcie->of_data->has_ltr_req_fix) {
1908 val = appl_readl(pcie, APPL_LTR_MSG_2);
1910 appl_writel(pcie, val, APPL_LTR_MSG_2);
1914 val = appl_readl(pcie, APPL_CTRL);
1916 appl_writel(pcie, val, APPL_CTRL);
1918 pcie->ep_state = EP_STATE_ENABLED;
1924 reset_control_assert(pcie->core_rst);
1925 tegra_pcie_disable_phy(pcie);
1927 reset_control_assert(pcie->core_apb_rst);
1929 clk_disable_unprepare(pcie->core_clk);
1931 tegra_pcie_bpmp_set_pll_state(pcie, false);
1933 tegra_pcie_bpmp_set_ctrl_state(pcie, false);
1940 struct tegra_pcie_dw *pcie = arg;
1942 if (gpiod_get_value(pcie->pex_rst_gpiod))
1943 pex_ep_event_pex_rst_assert(pcie);
1945 pex_ep_event_pex_rst_deassert(pcie);
1950 static int tegra_pcie_ep_raise_intx_irq(struct tegra_pcie_dw *pcie, u16 irq)
1956 appl_writel(pcie, 1, APPL_LEGACY_INTX);
1958 appl_writel(pcie, 0, APPL_LEGACY_INTX);
1962 static int tegra_pcie_ep_raise_msi_irq(struct tegra_pcie_dw *pcie, u16 irq)
1967 appl_writel(pcie, BIT(irq), APPL_MSI_CTRL_1);
1972 static int tegra_pcie_ep_raise_msix_irq(struct tegra_pcie_dw *pcie, u16 irq)
1974 struct dw_pcie_ep *ep = &pcie->pci.ep;
1985 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
1989 return tegra_pcie_ep_raise_intx_irq(pcie, interrupt_num);
1992 return tegra_pcie_ep_raise_msi_irq(pcie, interrupt_num);
1995 return tegra_pcie_ep_raise_msix_irq(pcie, interrupt_num);
2030 static int tegra_pcie_config_ep(struct tegra_pcie_dw *pcie,
2033 struct dw_pcie *pci = &pcie->pci;
2034 struct device *dev = pcie->dev;
2044 ret = gpiod_set_debounce(pcie->pex_rst_gpiod, PERST_DEBOUNCE_TIME);
2051 ret = gpiod_to_irq(pcie->pex_rst_gpiod);
2056 pcie->pex_rst_irq = (unsigned int)ret;
2059 pcie->cid);
2065 irq_set_status_flags(pcie->pex_rst_irq, IRQ_NOAUTOEN);
2067 pcie->ep_state = EP_STATE_DISABLED;
2069 ret = devm_request_threaded_irq(dev, pcie->pex_rst_irq, NULL,
2073 name, (void *)pcie);
2097 struct tegra_pcie_dw *pcie;
2107 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
2108 if (!pcie)
2111 pci = &pcie->pci;
2114 pcie->dev = &pdev->dev;
2115 pcie->of_data = (struct tegra_pcie_dw_of_data *)data;
2116 pci->n_fts[0] = pcie->of_data->n_fts[0];
2117 pci->n_fts[1] = pcie->of_data->n_fts[1];
2121 ret = tegra_pcie_dw_parse_dt(pcie);
2134 ret = tegra_pcie_get_slot_regulators(pcie);
2147 if (pcie->pex_refclk_sel_gpiod)
2148 gpiod_set_value(pcie->pex_refclk_sel_gpiod, 1);
2150 pcie->pex_ctl_supply = devm_regulator_get(dev, "vddio-pex-ctl");
2151 if (IS_ERR(pcie->pex_ctl_supply)) {
2152 ret = PTR_ERR(pcie->pex_ctl_supply);
2155 PTR_ERR(pcie->pex_ctl_supply));
2159 pcie->core_clk = devm_clk_get(dev, "core");
2160 if (IS_ERR(pcie->core_clk)) {
2162 PTR_ERR(pcie->core_clk));
2163 return PTR_ERR(pcie->core_clk);
2166 pcie->appl_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2168 if (!pcie->appl_res) {
2173 pcie->appl_base = devm_ioremap_resource(dev, pcie->appl_res);
2174 if (IS_ERR(pcie->appl_base))
2175 return PTR_ERR(pcie->appl_base);
2177 pcie->core_apb_rst = devm_reset_control_get(dev, "apb");
2178 if (IS_ERR(pcie->core_apb_rst)) {
2180 PTR_ERR(pcie->core_apb_rst));
2181 return PTR_ERR(pcie->core_apb_rst);
2184 phys = devm_kcalloc(dev, pcie->phy_count, sizeof(*phys), GFP_KERNEL);
2188 for (i = 0; i < pcie->phy_count; i++) {
2204 pcie->phys = phys;
2212 pcie->atu_dma_res = atu_dma_res;
2219 pcie->core_rst = devm_reset_control_get(dev, "core");
2220 if (IS_ERR(pcie->core_rst)) {
2222 PTR_ERR(pcie->core_rst));
2223 return PTR_ERR(pcie->core_rst);
2230 pcie->bpmp = tegra_bpmp_get(dev);
2231 if (IS_ERR(pcie->bpmp))
2232 return PTR_ERR(pcie->bpmp);
2234 platform_set_drvdata(pdev, pcie);
2236 pcie->icc_path = devm_of_icc_get(&pdev->dev, "write");
2237 ret = PTR_ERR_OR_ZERO(pcie->icc_path);
2239 tegra_bpmp_put(pcie->bpmp);
2244 switch (pcie->of_data->mode) {
2247 IRQF_SHARED, "tegra-pcie-intr", pcie);
2254 ret = tegra_pcie_config_rp(pcie);
2266 "tegra-pcie-ep-intr", pcie);
2273 ret = tegra_pcie_config_ep(pcie, pdev);
2280 pcie->of_data->mode);
2284 tegra_bpmp_put(pcie->bpmp);
2290 struct tegra_pcie_dw *pcie = platform_get_drvdata(pdev);
2292 if (pcie->of_data->mode == DW_PCIE_RC_TYPE) {
2293 if (!pcie->link_state)
2296 debugfs_remove_recursive(pcie->debugfs);
2297 tegra_pcie_deinit_controller(pcie);
2298 pm_runtime_put_sync(pcie->dev);
2300 disable_irq(pcie->pex_rst_irq);
2301 pex_ep_event_pex_rst_assert(pcie);
2304 pm_runtime_disable(pcie->dev);
2305 tegra_bpmp_put(pcie->bpmp);
2306 if (pcie->pex_refclk_sel_gpiod)
2307 gpiod_set_value(pcie->pex_refclk_sel_gpiod, 0);
2312 struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
2315 if (pcie->of_data->mode == DW_PCIE_EP_TYPE) {
2320 if (!pcie->link_state)
2324 if (!pcie->of_data->has_sbr_reset_fix) {
2325 val = appl_readl(pcie, APPL_CTRL);
2329 appl_writel(pcie, val, APPL_CTRL);
2337 struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
2339 if (!pcie->link_state)
2342 tegra_pcie_downstream_dev_to_D0(pcie);
2343 tegra_pcie_dw_pme_turnoff(pcie);
2344 tegra_pcie_unconfig_controller(pcie);
2351 struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
2354 if (!pcie->link_state)
2357 ret = tegra_pcie_config_controller(pcie, true);
2361 ret = tegra_pcie_dw_host_init(&pcie->pci.pp);
2367 dw_pcie_setup_rc(&pcie->pci.pp);
2369 ret = tegra_pcie_dw_start_link(&pcie->pci);
2376 tegra_pcie_unconfig_controller(pcie);
2382 struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
2385 if (pcie->of_data->mode == DW_PCIE_EP_TYPE) {
2390 if (!pcie->link_state)
2394 if (!pcie->of_data->has_sbr_reset_fix) {
2395 val = appl_readl(pcie, APPL_CTRL);
2401 appl_writel(pcie, val, APPL_CTRL);
2409 struct tegra_pcie_dw *pcie = platform_get_drvdata(pdev);
2411 if (pcie->of_data->mode == DW_PCIE_RC_TYPE) {
2412 if (!pcie->link_state)
2415 debugfs_remove_recursive(pcie->debugfs);
2416 tegra_pcie_downstream_dev_to_D0(pcie);
2418 disable_irq(pcie->pci.pp.irq);
2420 disable_irq(pcie->pci.pp.msi_irq[0]);
2422 tegra_pcie_dw_pme_turnoff(pcie);
2423 tegra_pcie_unconfig_controller(pcie);
2424 pm_runtime_put_sync(pcie->dev);
2426 disable_irq(pcie->pex_rst_irq);
2427 pex_ep_event_pex_rst_assert(pcie);
2474 .compatible = "nvidia,tegra194-pcie",
2478 .compatible = "nvidia,tegra194-pcie-ep",
2482 .compatible = "nvidia,tegra234-pcie",
2486 .compatible = "nvidia,tegra234-pcie-ep",
2504 .name = "tegra194-pcie",